公开(公告)号：US11456306B2

公开(公告)日：2022-09-27

申请号：US17100954

申请日：2020-11-23

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Bong Woong Mun ,  Jeoung Mo Koo

IPC分类号： H01L27/11521 ,  H01L49/02 ,  H01L29/06 ,  H01L29/788 ,  H01L29/66

摘要： A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.

公开(公告)号：US11444168B2

公开(公告)日：2022-09-13

申请号：US17086501

申请日：2020-11-02

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Jiacheng Lei ,  James Jerry Joseph ,  Khee Yong Lim ,  Lulu Peng ,  Lawrence Selvaraj Susai

IPC分类号： H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10

摘要： A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.

公开(公告)号：US11380677B2

公开(公告)日：2022-07-05

申请号：US16860087

申请日：2020-04-28

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Jiacheng Lei ,  Lawrence Selvaraj Susai

IPC分类号： H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L21/8252 ,  H01L29/66 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/872

摘要： According to various embodiments, a transistor device may include a semiconductor structure having a trench formed therein. The semiconductor structure may include a buffer layer and a barrier layer arranged over the buffer layer. The trench may extend at least to the buffer layer. The transistor device may include a source terminal, a drain terminal, and a gate terminal arranged between the source terminal and the drain terminal. The gate terminal may extend into the trench. The transistor device may include an electrode component. The electrode component may include an electrode. The electrode component may extend into the trench where the electrode component is separated from the gate terminal. The electrode component may contact a side wall of the trench.

公开(公告)号：US20220205948A1

公开(公告)日：2022-06-30

申请号：US17699219

申请日：2022-03-21

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Lanxiang WANG ,  Bin LIU ,  Eng Huat TOH ,  Shyue Seng TAN ,  Kiok Boone Elgin QUEK

IPC分类号： G01N27/414 ,  H01L29/16 ,  H01L29/04

摘要： According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.

公开(公告)号：US11374135B2

公开(公告)日：2022-06-28

申请号：US16556333

申请日：2019-08-30

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Lanxiang Wang ,  Shyue Seng Tan ,  Eng Huat Toh

IPC分类号： H01L31/02 ,  H01L31/028 ,  H01L31/18 ,  H01L31/0392 ,  H01L31/107 ,  H01L31/0312

摘要： A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.

公开(公告)号：US11372061B2

公开(公告)日：2022-06-28

申请号：US16817623

申请日：2020-03-13

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Yongshun Sun ,  Eng Huat Toh ,  Ping Zheng

IPC分类号： G01R33/07 ,  G01R33/00 ,  H01L43/14 ,  H01L43/06 ,  H01L43/04

摘要： A Hall effect sensor device may be provided, including one or more sensor structures. Each sensor structure may include: a base layer having a first conductivity type; a Hall plate region having a second conductivity type opposite from the first conductivity type arranged above the base layer; a first isolating region arranged around and adjoining the Hall plate region, and contacting the base layer; a plurality of second isolating regions arranged within the Hall plate region; and a plurality of terminal regions arranged within the Hall plate region. The first and second isolating regions may include electrically insulating material, and each neighboring pair of terminal regions may be electrically isolated from each other by one of the second isolating regions.

公开(公告)号：US20220181479A1

公开(公告)日：2022-06-09

申请号：US17115724

申请日：2020-12-08

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： CHOR SHU CHENG ,  HANDOKO LINEWIH ,  SIOW LEE CHWA

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

摘要： A semiconductor device is provided. The semiconductor device comprises a substrate having a wide bandgap semiconductor material and an epitaxial layer arranged over a first surface of the substrate. A source region having a first conductivity type may be arranged in the epitaxial layer. A well region having a second conductivity type may be laterally adjacent to the source region. The first conductivity type may be different from the second conductivity type. A gate dielectric layer may be arranged over the well region. A field dielectric layer may be arranged over the epitaxial layer adjacent to the well region.

公开(公告)号：US20220181474A1

公开(公告)日：2022-06-09

申请号：US17114391

申请日：2020-12-07

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： PRANTIK MAHAJAN ,  RAUNAK KUMAR ,  KYONG JIN HWANG ,  ROBERT JR GAUTHIER JR

IPC分类号： H01L29/74 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06

摘要： A silicon controlled rectifier is provided. The silicon controlled rectifier comprises a substrate and a first n-well in the substrate. A p+ anode region may be arranged in the first n-well in the substrate. A first p-well may be arranged in the first n-well in the substrate. An n+ cathode region may be arranged in the first p-well in the substrate. A field oxide layer may be arranged over a first portion of the first p-well. A first gate electrode layer may extend over a second portion of the first p-well and over a portion of the field oxide layer.

公开(公告)号：US20220140096A1

公开(公告)日：2022-05-05

申请号：US17086501

申请日：2020-11-02

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Jiacheng LEI ,  James JERRY JOSEPH ,  Khee Yong LIM ,  Lulu PENG ,  Lawrence Selvaraj SUSAI

IPC分类号： H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778 ,  H01L29/40

摘要： A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.

公开(公告)号：US20220139929A1

公开(公告)日：2022-05-05

申请号：US17087683

申请日：2020-11-03

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Xinshu CAI ,  Yongshun SUN ,  Lanxiang WANG ,  Eng Huat TOH ,  Shyue Seng TAN

IPC分类号： H01L27/1156 ,  H01L29/06

摘要： A memory structure may be provided, including a substrate, and a first well region, a second well region, and a third well region arranged within the substrate, where the first well region and the third well region may have a first conductivity type, and the second well region may have a second conductivity type different from the first conductivity type, and where the second well region may be arranged laterally between the first well region and the third well region. The memory structure may further include a first gate structure and a second gate structure arranged over the second well region. The first gate structure may extend over the third well region and the second gate structure may extend over the first well region.