Abstract:
A device receives a standard command. The device judges whether an address field and/or a data length field and/or a data field of the standard command includes at least one of a vendor command, a vendor data and a checkword. The device judges whether the address field and/or a data length field and/or the data field of the standard command matches a vendor predetermined pattern. If matched, the device performs a vendor operation based on the vendor command and/or the vendor data of the standard command.
Abstract:
A transmission system includes a transmission apparatus, a first electronic device and a second electronic device electrically connected to one another. The first electronic includes a composite driver, a first application program, a first display image and a virtual display device. The first composite driver emulates the virtual display device according to the first display image. The second electronic device includes a second application program and a second display image. The transmission interface includes a transmission controller and two transmission interfaces. The two transmission interfaces are connected to the first electronic device and the second electronic device, respectively. When the first application program transmits output data corresponding to the virtual display device via the two transmission interfaces and the transmission controller to the second application program, a virtual display image corresponding to the first display image is presented on the second display image.
Abstract:
A USB interface provided with USB host/device function and its control method is disclosed. The USB interface includes a control unit, a USB host, a USB device, a memory, a port router and a plurality of connection ports. The control unit is used to define the connection ports to be either an upstream port or downstream port. It also controls signal flows within the USB control interface. The signal flows are provided for the USB host and the USB device. The memory is used to store data during the operation of the USB control interface. The USB host is coupled to an external device via the port router, and the USB device is coupled to an external host via the port router.
Abstract:
Provided is a bridge coupled between an external host and an external storage device. The bridge includes a first interface, an encoder, a memory device, a decoder and a second interface. The first interface is coupled to the external host and receives a first data from an external host. The encoder is coupled to the first interface and compresses the first data by undistorted compression for producing a second data. The memory device is coupled to the encoder and temporally stores the second data produced by the encoder. The decoder is coupled to the memory device and decompresses the second data stored in the memory device for producing a third data. The third data and the first data are substantially the same. The second interface is coupled between the decoder and the external storage device and outputs the third data transmitted from the decoder to the external storage device.
Abstract:
A voltage regulator includes a comparator, a first voltage output unit, a second voltage output unit, a third voltage output unit, a first switch and a second switch. The voltage regulator receives an operating voltage and a reference voltage generated by a reference voltage generator, and then outputs a corresponding output voltage. The voltage regulator of the present invention can provide an operation mode, a suspend mode and a standby mode and can be switched among these modes to provide corresponding current driving capacity for respective operation states. When in the operation mode, the voltage regulator can supply a great current. When in the suspend mode, the voltage regulator consumes less power. When in the standby mode, the voltage regulator consumes even less power.
Abstract:
A global positioning System receiver and a correlating circuit thereof are disclosed. They sequentially and in parallel generate the portion of bits of the C/A code representing the satellite, sequentially and in parallel generate the portion of bits of the corrected frequency code of Doppler effect, and sequentially outputs the portion of bits of the C/A code and the corrected frequency code therefrom for multiplying the data and the IF data and for adding the multiplications therefrom for generating the total addition values.
Abstract:
A phase-difference detecting method is for detecting phase difference between a first signal and a second signal of the same frequency. First, generate a detection signal. Next, sample the detection signal respectively according to the first signal and the second signal to obtain a first sample value and a second sample value. Then, determine whether a determination condition that the first and the second sample values are respectively equal to the previous first and second sample values is satisfied. When the determination condition is unsatisfied for the first time, record a delay time of the detection signal as a first time. When the determination condition is unsatisfied for the second time, record a delay time of the detection signal as a second time. Obtain the phase difference between the first signal and the second signal according to the first time and the second time.
Abstract:
A system and method of high speed clock/data recovery, which is used to recover the high speed clock/data through oversampling technique, wherein the internal clock with frequency lower than the high speed data is used for data recovery. Only three clocks are used in the digital circuit without involving all the oversampling clock phases to make the design timing complicated and critical. The system and method provide a simple clock structure to implement the digital circuit of high speed clock/data recovery in a robust and easy way. Furthermore a phase selection mechanism which decides the clock phase of the high speed data is provided as well.
Abstract:
A training method of a digital-analog converter is provided. The digital-analog converter comprises a plurality of parallel capacitors, each of which is floatingly coupled to a plurality of correcting capacitors. Two voltages outputted from the digital-analog converter are received and compared. When a latter output voltage is lower than or equal to a former output voltage, the correcting capacitor is used to correct the capacitor corresponding to the latter output voltage until the latter output voltage is higher than the former output voltage. When the latter output voltage is higher than the former output voltage, a new voltage is outputted from the digital-analog convert and compared with the latter output voltage. The steps of comparing and correcting are repeated until every latter output voltage is higher than every former output voltage.
Abstract:
A motor drive circuit and method with frequency setting and correcting functions. The drive circuit includes a speed control device, which simultaneously receives a sense signal and a rotation frequency signal. A pulse width modulation signal capable of modulating a duty ratio may be generated by a pulse width modulation method. The pulse width modulation signal is then transferred to a drive timing controller that generates a timing control signal to control output timing of a power drive signal for the drive circuit. Meanwhile, a sensor is used to detect a motor and to generate a correction sense signal, which is immediately fed back to the speed control device to form a closed loop control, so that the rotation frequency of the motor may be automatically corrected and set.