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    AUDIO AMPLIFIER WITH EMBEDDED BUCK CONTROLLER FOR CLASS-G APPLICATION
    51.
    发明公开
    AUDIO AMPLIFIER WITH EMBEDDED BUCK CONTROLLER FOR CLASS-G APPLICATION 审中-公开

    公开(公告)号：US20240056046A1

    公开(公告)日：2024-02-15

    申请号：US18493282

    申请日：2023-10-24

    Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.

    Inventor： XiangSheng Li ,  Ru Feng Du

    IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00 ,  H04R29/00

    CPC classification number: H03G3/3005 ,  H03F3/187 ,  H04R3/00 ,  H04R29/00 ,  H03F2200/03 ,  H03G2201/103

    Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.

    Audio amplifier with embedded buck controller for class-G application
    52.
    发明授权
    Audio amplifier with embedded buck controller for class-G application 有权

    公开(公告)号：US11831286B2

    公开(公告)日：2023-11-28

    申请号：US17241980

    申请日：2021-04-27

    Applicant: STMicroelectronics (Shenzhen) R & D Co. Ltd.

    Inventor： XiangSheng Li ,  Ru Feng Du

    IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00 ,  H04R29/00

    CPC classification number: H03G3/3005 ,  H03F3/187 ,  H04R3/00 ,  H04R29/00 ,  H03F2200/03 ,  H03G2201/103

    Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.

    Inverter and method for measuring phase currents in an electric machine
    53.
    发明授权
    Inverter and method for measuring phase currents in an electric machine 有权

    公开(公告)号：US11105836B2

    公开(公告)日：2021-08-31

    申请号：US16746444

    申请日：2020-01-17

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Dino Costanzo ,  Cheng Pan Cai ,  Xi Yu Xu

    IPC: G01R19/25 ,  H02P27/08 ,  H02M1/00 ,  G01R15/14 ,  H02M7/5387

    Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

    AUDIO AMPLIFIER WITH EMBEDDED BUCK CONTROLLER FOR CLASS-G APPLICATION
    54.
    发明申请
    AUDIO AMPLIFIER WITH EMBEDDED BUCK CONTROLLER FOR CLASS-G APPLICATION 有权

    公开(公告)号：US20210250010A1

    公开(公告)日：2021-08-12

    申请号：US17241980

    申请日：2021-04-27

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd.

    Inventor： XiangSheng Li ,  Ru Feng Du

    IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00 ,  H04R29/00

    Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.

    ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTING ELECTRONIC CIRCUITS
    55.
    发明申请
    ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTING ELECTRONIC CIRCUITS 有权

    公开(公告)号：US20210232174A1

    公开(公告)日：2021-07-29

    申请号：US17159511

    申请日：2021-01-27

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Ignazio PISELLO ,  Yu Yong WANG ,  Dario ARENA ,  Qi Yu LIU

    IPC: G06F1/06 ,  G01R31/317

    Abstract: A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.

    Methods and circuits to reduce pop noise in an audio device
    56.
    发明授权
    Methods and circuits to reduce pop noise in an audio device 有权

    公开(公告)号：US10530309B2

    公开(公告)日：2020-01-07

    申请号：US16222281

    申请日：2018-12-17

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Ru Feng Du ,  Qi Yu Liu

    IPC: H03F1/32 ,  H03F1/30 ,  H03F1/02 ,  H03F3/45 ,  H03F3/183 ,  H03F3/185 ,  H03F3/187 ,  H03F3/21 ,  H03F3/217 ,  H03G3/34 ,  H04R3/00

    Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.

    Current limiting circuit
    57.
    发明授权
    Current limiting circuit 有权

    公开(公告)号：US10209725B2

    公开(公告)日：2019-02-19

    申请号：US15675872

    申请日：2017-08-14

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Ni Zeng

    IPC: G05F1/573

    Abstract: A current limiting circuit includes a current sensing module that is configured to sense an output current of a power transistor and to generate a corresponding sensing current which is proportional to the output current. A first current limiting module coupled to the current sensing module is configured to generate a first limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a first current level. A second current limiting module coupled to the current sensing module is configured to generate a second limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a second current level. A converting module coupled to the first and second current limiting modules and the power transistor controls a gate voltage of the power transistor based at least on the first and second limiting currents.

    Bidirectional voltage differentiator circuit
    60.
    发明授权
    Bidirectional voltage differentiator circuit 有权

    公开(公告)号：US09891250B2

    公开(公告)日：2018-02-13

    申请号：US15641088

    申请日：2017-07-03

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Yijun Duan

    IPC: G01R19/12 ,  H03L7/00 ,  H05B33/08 ,  G01R19/165

    CPC classification number: G01R19/12 ,  G01R19/16557 ,  H05B33/0845 ,  H05B33/0887

    Abstract: A bidirectional voltage differentiator circuit comprises start-up circuitry, sensing circuitry, and output circuitry coupled to logic circuitry. The start-up circuitry acts to start-up the sensing circuitry when the circuit is powered on, and accelerates the response of the sensing circuitry thereafter. The sensing circuitry senses variation in an input voltage applied to an input node. Responsive to the voltage variation sensed by the sensing circuitry, the output circuitry produces a state change at a first or second output node. The logic circuitry receives the states of the output nodes and produces a logic output signal to indicate the occurrence of the variation sensed in the input voltage. The voltage sensing circuit is operable to sense variation of the input voltage regardless of whether the voltage is rising or falling and without regard to the DC value of the input voltage.

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