公开(公告)号：US20060031273A1

公开(公告)日：2006-02-09

申请号：US10914046

申请日：2004-08-06

Applicant: Malcolm Drummond

Inventor： Malcolm Drummond

IPC: G06F1/02

CPC classification number: H01J37/32174 ,  G06F1/0328 ,  G06F1/0342 ,  H01J37/32165

Abstract: A plasma control system including a direct digital synthesizer (DDS) for generating more than one individual RF power signal, where the individual RF power signals are combined to define a combined RF power signal. The DDS includes an accumulator which receives a phase increment signal that defines a frequency of a frequency signal generated by the accumulator. The frequency signal is split and input to a plurality of adders. Each adder receives a phase offset signal that defines a phase shift of the frequency signal input to that particular adder. The phase increment signal and phase offset may be stored to reduce the startup portion of the plasma control system.

公开(公告)号：US20060009938A1

公开(公告)日：2006-01-12

申请号：US11158673

申请日：2005-06-21

Applicant: Tseng Roger ,  Chih Wang

Inventor： Tseng Roger ,  Chih Wang

IPC: G06F19/00

CPC classification number: G01R31/31709 ,  G01R29/26 ,  G06F1/0328

Abstract: A digital jitter synthesizer includes a signal generation unit, a tuning frequency optional unit, and a random option unit. The tuning frequency optional unit is able to output a frequency control value, and leads the signal generation unit tune the frequency of an output signal based on the frequency control value; then the signal with the frequency can be fed back to the random optional unit to lead the tuning frequency optional unit generate the other frequency control value randomly to control the signal generation unit for tuning the output signal to the other frequency then to generate an output signal with jitter effect.

Abstract translation: 数字抖动合成器包括信号产生单元，调谐频率可选单元和随机选项单元。 调谐频率可选单元能够输出频率控制值，并使信号发生单元根据频率控制值调整输出信号的频率; 那么具有频率的信号可以反馈到随机可选单元以引导调谐频率可选单元随机生成另一个频率控制值，以控制信号生成单元，以将输出信号调谐到另一个频率，然后生成输出信号 具有抖动效应。

公开(公告)号：US20050248374A1

公开(公告)日：2005-11-10

申请号：US10842746

申请日：2004-05-10

Applicant: Eric Kushnick

Inventor： Eric Kushnick

IPC: G01R31/28 ,  G01R31/319 ,  G06F1/03 ,  H03B21/02

CPC classification number: G06F1/0328 ,  G01R31/31907 ,  G01R31/31917 ,  G06F2101/04

Abstract: The present invention is directed to the use of a DDS to generate a high purity reference signal with high frequency resolution by switching a frequency tuning word (FTW) between particular values for particular time durations to produce two or more closely spaced frequencies that appear at the DDS output as a single frequency. Given a DDS switching between F1 and F2 such that F1 is present for time T1 and F2 is present for time T2, with the total period of the repeating pattern being T=T1+T2, in order for the output of the DDS to produce a single high-purity frequency that is the time-weighted average of the alternating frequencies, the condition |F1−F2|

Abstract translation: 本发明涉及使用DDS通过在特定时间间隔内的特定值之间切换频率调谐字（FTW）来产生具有高频分辨率的高纯度参考信号，以产生两 DDS输出为单频。 给定F1和F2之间的DDS切换，使得F1存在时间T1，F2存在于时间T2，重复模式的总周期为T = T1 + T2，以便DDS的输出产生 单个高纯度频率是交变频率的时间加权平均值，条件| F1-F2 | << pi / T必须满足。 时间加权平均频率Favg =（T1.F1 + T2.F2）/（T + T2）。 通过适当选择T1和T2，Favg可以设置为这两个频率之间的任何频率。

公开(公告)号：US20050135525A1

公开(公告)日：2005-06-23

申请号：US10744039

申请日：2003-12-23

Applicant: Jason Messier

Inventor： Jason Messier

IPC: G06F1/08 ,  G01R31/00 ,  G01R31/28 ,  G01R31/3167 ,  G06F1/03 ,  H03L7/00 ,  H04L7/00

CPC classification number: G06F1/0328 ,  H03L7/00

Abstract: A test system using direct digital synthesis for generation of a spectrally pure, agile clock. The clock is used in analog and digital instruments in automatic test system. A DDS circuit is synchronized to the tester system clock because it is clocked by a DDS clock generated from the system clock. Accumulated phase error is reduced through the use of a parallel accumulator that tracks accumulated phase relative to the system clock. At coincidence points, the accumulated phase in the DDS accumulator is reset to the value in the system accumulator.

Abstract translation: 一种使用直接数字合成产生光谱纯，敏捷时钟的测试系统。 时钟用于自动测试系统中的模拟和数字仪器。 DDS电路与测试仪系统时钟同步，因为它是由系统时钟产生的DDS时钟计时的。 通过使用跟踪累积相位相对于系统时钟的并行累加器来减少累积相位误差。 在重合点，DDS累加器中的累加相复位为系统累加器中的值。

公开(公告)号：US20050135514A1

公开(公告)日：2005-06-23

申请号：US11012192

申请日：2004-12-16

Applicant: Akihiro Suzuki ,  Hiroshi Sonobe

Inventor： Akihiro Suzuki ,  Hiroshi Sonobe

IPC: H04N5/04 ,  G06F1/03 ,  H03L7/107 ,  H04B1/38 ,  H04L7/033 ,  H04N5/06 ,  H04N5/08 ,  H04N5/12

CPC classification number: G06F1/0328 ,  H04N5/126

Abstract: Provided is a synchronous clock generation apparatus which comprises a multiplier for multiplying a horizontal synchronizing signal by a horizontal synchronizing pulse signal to generate multiplication data, a gain variable digital LPF for extracting only DC components from the multiplication data and capable of performing gain adjustment, and a controller for calculating gain adjustment data, lock center frequency setting data, and LPF gain adjustment data on the basis of the correction data, and which detects an amount of deviation from the lock center frequency and an amount of variation, and displaces the lock center frequency and shifts the lock range along the frequency axis to enlarge the apparent lock range when the amount of deviation is large, and reduces the gain to improve lock precision when the amount of variation is small, without expanding bits in the circuit configuration.

Abstract translation: 提供了一种同步时钟发生装置，其包括用于将水平同步信号乘以水平同步脉冲信号以产生乘法数据的乘法器，用于从乘法数据中仅提取DC分量并且能够执行增益调整的增益可变数字LPF，以及 基于校正数据计算增益调整数据，锁定中心频率设定数据和LPF增益调整数据的控制器，其检测与锁定中心频率和变化量的偏差量，并且使锁定中心 频率并沿着频率轴移动锁定范围，以在偏差量大时扩大视在锁定范围，并且当变化量小时，降低增益以提高锁定精度，而不扩展电路配置中的位。

公开(公告)号：US20050134330A1

公开(公告)日：2005-06-23

申请号：US10739591

申请日：2003-12-18

Applicant: Steven Sullivan ,  Raymond Veith ,  Iwao Akiyama ,  Yasumasa Fujisawa

Inventor： Steven Sullivan ,  Raymond Veith ,  Iwao Akiyama ,  Yasumasa Fujisawa

IPC: H03K3/64 ,  G06F1/03 ,  H03B1/00

CPC classification number: G06F1/0328

Abstract: A DDS pulse generator has an accumulator that accumulates a phase increment value to produce phase accumulator values, and has a lookup table that contains a digital representation of a pulse waveform such that a pulse output signal is produced from the lookup table in response to the phase accumulator values. To change a period of the pulse output signal without changing edge positions a programmable modulo value is used. An address mapper is situated between the accumulator and address lines of the lookup table to map the rising and falling edge portions of the phase accumulator values into large regions of the lookup table, while phase accumulator values corresponding to high and low logic levels are mapped into small regions of the lookup table. The resulting pulse output signal has easily independently controlled period and pulse width as well as rising and falling edge speeds. By making better use of the lookup table it is possible to generate very narrow pulses with low repetition rates or pulses in which the rise time and fall time are very different from the period.

Abstract translation: DDS脉冲发生器具有累加相位增量值以产生相位累加器值的累加器，并且具有包含脉冲波形的数字表示的查找表，使得响应于相位从查找表产生脉冲输出信号 累加器值。 为了改变脉冲输出信号的周期而不改变边沿位置，使用可编程的模数值。 地址映射器位于查找表的累加器和地址线之间，以将相位累加器值的上升沿和下降沿部分映射到查找表的大区域，而对应于高逻辑电平和低逻辑电平的相位累加器值映射到 查找表的小区域。 所产生的脉冲输出信号容易独立地控制周期和脉冲宽度以及上升和下降沿速度。 通过更好地利用查找表，可以产生具有低重复率或脉冲的非常窄的脉冲，其中上升时间和下降时间与周期非常不同。

公开(公告)号：US06674380B1

公开(公告)日：2004-01-06

申请号：US10290943

申请日：2002-11-08

Applicant: Kenneth Alan Essenwanger

Inventor： Kenneth Alan Essenwanger

IPC: H03M162

CPC classification number: G06F1/0328 ,  G06F1/0353

Abstract: Differential heating is avoided by a digital to analog converter for generating analog cyclical waveforms having a period. The cyclical waveforms are generated by conversion of a sequence of step wise linearly incrementing digital phase words presented during the period for conversion. The digital to analog converter has a clock for operating conversion timing within the digital to analog converter. The clock generates a clock pulse for conversion of each of the digital phase words by said digital to analog converter while generating the cyclical waveform. A lookup read only memory for converting each of the incrementing digital phase words within the period into a plurality of ON commands to be used by a plurality of current sources. The plurality of ON commands are timed to generate the cyclical waveforms and have nearly equal time duration approximating a 50 percent duty cycle. The cyclical waveform has one or more non-linear portions reflected in the content of the read only memory.

Abstract translation: 用于产生具有周期的模拟周期波形的数模转换器避免了差分加热。 循环波形是通过在转换周期期间呈现的逐步线性递增数字相位字的序列的转换产生的。 数模转换器具有用于在数模转换器内进行转换时序的时钟。 时钟产生时钟脉冲，用于在产生循环波形的同时，通过所述数模转换器转换每个数字相位字。一种查找只读存储器，用于将周期内的递增数字相位字转换为多个ON命令 被多个电流源使用。 多个ON命令被定时以产生循环波形并且具有接近50％占空比的近似相等的持续时间。循环波形具有在只读存储器的内容中反映的一个或多个非线性部分。

公开(公告)号：US06597208B1

公开(公告)日：2003-07-22

申请号：US09926587

申请日：2001-11-21

Applicant: Pascal Gabet ,  Jean-Luc De Gouy

Inventor： Pascal Gabet ,  Jean-Luc De Gouy

IPC: H03D324

CPC classification number: H04L27/122 ,  G06F1/0328 ,  G06F7/72

Abstract: A direct digital frequency-synthesis device includes a modulo-M coherent accumulator that generates a first phase law from a frequency-control word. A table, addressed by a second phase law derived from the first phase law, generates a digital sinusoidal signal. A digital/analog converter converts the digital sinusoidal signal into an analog sinusoidal signal. A filter filters the analog sinusoidal signal. And, a divider divides the filtered signal. The divider has a lower order than M and has a synchronization input driven by a synchronization pulse for re-synchronizing the signal after division, the synchronization pulse being derived from the phase law. Such a device may find particular application to digital synthesizers for radar.

Abstract translation: 直接数字频率合成装置包括模M相干累加器，其从频率控制字产生第一相位定律。 由第一相定律得出的第二相定律寻址的表产生数字正弦信号。 数字/模拟转换器将数字正弦信号转换为模拟正弦信号。 滤波器滤波模拟正弦信号。 并且，除法器分割滤波后的信号。 除法器具有比M更低的阶数，并且具有由同步脉冲驱动的同步输入，用于重新同步分频后的信号，同步脉冲从相位律导出。 这样的装置可以发现用于雷达的数字合成器的特定应用。

公开(公告)号：US06587863B1

公开(公告)日：2003-07-01

申请号：US09605099

申请日：2000-06-27

Applicant: Ken Gentile ,  John Kornblum

Inventor： Ken Gentile ,  John Kornblum

IPC: G06F102

CPC classification number: G06F1/0328

Abstract: Direct digital synthesis (DDS) methods and structures are provided that increase DDS output frequencies fout without requiring a corresponding increase in the rate fclk at which DDS structures must operate. An exemplary method generates a periodic stream of digital words at a clock frequency fclk wherein the words represent respective amplitudes of a predetermined periodic waveform, the periodic stream has a period P and the digital words are spaced by a phase step &phgr;s. This method comprises the steps of a) with a count capacity C, counting modulo n&phgr;s at a reduced clock frequency (1/n)fclk to thereby generate a primary substream of digital words, b) phase offsetting the primary substream to form n−1 secondary substreams of digital words wherein the primary and secondary substreams are phase spaced by the phase step &phgr;s, c) converting the digital words of each of the primary, and secondary substreams to converted digital words that represent respective amplitudes of the predetermined waveform, and d) interleaving the primary and secondary substreams to thereby form the periodic stream of digital words that occur at the clock frequency fclk.

Abstract translation: 提供直接数字合成（DDS）方法和结构，其增加DDS输出频率fout，而不需要DDS结构必须操作的速率fclk的相应增加。 一种示例性方法在时钟频率fclk处产生数字字的周期性流，其中字表示预定周期波形的各个幅度，周期流具有周期P，数字字由相位步长隔开。 该方法包括以下步骤：a）具有计数能力C，以降低的时钟频率（1 / n）fclk对模数nphis进行计数，从而产生数字字的主子流，b）相位偏移主子流以形成n-1 数字字的二次子流，其中主和次级子流由相位步长相位相隔，c）将主和次级子流中的每一个的数字字转换成表示预定波形的各个幅度的转换数字字，d ）对主流和次级流进行交织，从而形成在时钟频率fclk出现的数字字的周期流。

公开(公告)号：US20020075077A1

公开(公告)日：2002-06-20

申请号：US09988276

申请日：2001-11-19

Applicant: ASULAB S.A.

Inventor： Pierre-Andre Farine ,  Jean-Daniel Etienne ,  Ruud Riem-Vis ,  Elham Firouzi

IPC: H03L007/00

CPC classification number: G06F7/68 ,  G01S19/13 ,  G01S19/29 ,  G01S19/34 ,  G01S19/35 ,  G06F1/0328 ,  H04B2001/70706

Abstract: The numerically controlled oscillator (8) is mounted in particular in a radiofrequency signal receiver which further includes means (3) for receiving and shaping the radiofrequency signals, a correlation stage (4) and a clock signal generator. The oscillator receives at one input a clock signal with a first frequency (CLK) which clocks the oscillator operations, and a binary word of several bits (Nb) to provide at one output at least an output signal (Mb) with a frequency determined as a function of said binary word and the clock signal. The oscillator includes a first accumulation stage (12) for a first number of most-significant bits (Ob) of the binary word and a second accumulation stage (12) for a second number of least-significant bits (Pb) of said binary word. The first accumulation stage is clocked at the first clock frequency (CLK) to supply the determined frequency output signal (Mb), while the second stage is clocked at a second clock frequency (CLK/N) N times lower than the first clock frequency. Output bits (Qb) or binary signals from the second stage are multiplied by N to be introduced at the input of the first stage every N cycles of the clock signal at the first frequency (CLK).

Abstract translation: 数控振荡器（8）特别安装在射频信号接收机中，射频信号接收机还包括用于接收和整形射频信号的装置（3），相关级（4）和时钟信号发生器。 振荡器在一个输入处接收具有对振荡器操作进行时钟的第一频率（CLK）的时钟信号，以及几比特（Nb）的二进制字以在一个输出端提供至少一个输出信号（Mb），频率确定为 所述二进制字和时钟信号的功能。 所述振荡器包括用于所述二进制字的第一数量的最高有效位（Ob）的第一累积级（12）和用于所述二进制字的第二数量的最低有效位（Pb）的第二累积级（12） 。 以第一时钟频率（CLK）对第一累积级进行计时，以提供确定的频率输出信号（Mb），而第二级以比第一时钟频率低N倍的第二时钟频率（CLK / N）被计时。 来自第二级的输出位（Qb）或二进制信号乘以N，以在第一频率（CLK）处的每个N个周期的时钟信号在第一级的输入处被引入。