公开(公告)号：US20130077615A1

公开(公告)日：2013-03-28

申请号：US13241470

申请日：2011-09-23

申请人： Assaf Prihed ,  Shai Kalfon

发明人： Assaf Prihed ,  Shai Kalfon

IPC分类号： H04B7/216 ,  H04W88/00 ,  H04J13/00

CPC分类号： H03M13/2714

摘要： Described embodiments provide a wideband code division multiple access (W-CDMA) system, that employs an interleaving rule having a modified pruning algorithm. Interleaving, by pruning a sequence of bits in the W-CDMA system, includes determining a non-pruned interleaved vector having a length N. The determination of the non-pruned interleaved vector is based on a received length of an input vector from the sequence of bits. The input vector is padded. An interleaver generates a pre-pruned interleaved vector having a length equal to the length N, wherein the pre-pruned interleaved vector is a function of the padded input vector and the non-pruned interleaving vector. The interleaver prunes one or more elements from the pre-pruned interleaved vector based on a corresponding pruning indication in a pruning indication table, thereby providing a pruned interleaved vector as a portion of the interleaved sequence of bits.

摘要翻译： 所描述的实施例提供了一种使用具有修改的修剪算法的交织规则的宽带码分多址（W-CDMA）系统。 通过修剪W-CDMA系统中的一系列比特来交织，包括确定具有长度N的未修剪的交织向量。未修剪的交织向量的确定基于来自序列的输入向量的接收长度 的位。 填充输入向量。 交织器生成具有等于长度N的长度的预剪切交织向量，其中预剪切交织向量是填充输入向量和未修剪交织向量的函数。 交织器基于修剪指示表中的对应修剪指示，从预先剪切的交错向量中修剪一个或多个元素，从而提供修剪后的交织向量作为交织的比特序列的一部分。

公开(公告)号：US20110041042A1

公开(公告)日：2011-02-17

申请号：US12854528

申请日：2010-08-11

申请人： Jin Wook HAN ,  Yong Chan Kim

发明人： Jin Wook HAN ,  Yong Chan Kim

IPC分类号： H03M13/27 ,  G06F11/10

CPC分类号： H04L1/005 ,  H03M13/2714 ,  H03M13/2767 ,  H03M13/2789 ,  H03M13/6502 ,  H04L1/0055 ,  H04L1/0071

摘要： An apparatus and method for determining interleaved addresses of a turbo interleaver are disclosed. A new interleaving size of received data is compared with a previously-stored interleaving size. When the compared interleaving sizes are equal to each other, the received data is decoded using previously-stored interleaved addresses. When the compared interleaving sizes are different from each other, the received data is decoded using new interleaved addresses generated with the new interleaving size. The turbo interleaver generates interleaved addresses at minimum number of code blocks rather than every code block, resulting in reduction of decoding delay and improvement of decoding performance.

摘要翻译： 公开了一种用于确定turbo交织器的交织地址的装置和方法。 将接收数据的新的交织大小与先前存储的交织大小进行比较。 当比较的交织大小彼此相等时，使用先前存储的交织地址对接收到的数据进行解码。 当比较的交织大小彼此不同时，使用以新的交织大小生成的新的交织地址对接收到的数据进行解码。 turbo交织器以最小数量的码块而不是每个码块生成交织地址，导致解码延迟的减少和解码性能的提高。

公开(公告)号：US20100083072A1

公开(公告)日：2010-04-01

申请号：US12286359

申请日：2008-09-30

申请人： Mohit K. Prasad ,  Clark H. Jarvis

发明人： Mohit K. Prasad ,  Clark H. Jarvis

IPC分类号： H03M13/27 ,  G06F11/07

CPC分类号： H03M13/2771 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2957 ,  H04L1/0066 ,  H04L1/0071

摘要： Methods and corresponding systems in an interleaver include loading K symbol data, in a linear order, into a matrix memory having (R·C) storage locations corresponding R rows and C columns. A sequence of interleaved addresses is produced for reading the K symbol data in an interleaved order from the matrix memory. Next, (R·C)−K interleaved addresses are queued in a first-in-first-out (FIFO) memory. After queuing (R·C)−K interleaved addresses in the FIFO memory, symbol data is output using the interleaved addresses in the FIFO memory to address and output the symbol data in the matrix memory in the interleaved order. The FIFO memory can contain at least 234 memory locations.

摘要翻译： 交织器中的方法和对应系统包括将K符号数据以线性顺序加载到具有对应于R行和C列的（R·C）存储位置的矩阵存储器中。 产生用于从矩阵存储器以交错顺序读取K个符号数据的交织地址序列。 接下来，（R·C）-K交织地址在先进先出（FIFO）存储器中排队。 在FIFO存储器中排队（R·C）-K交错地址之后，使用FIFO存储器中的交错地址输出符号数据，以交错顺序对矩阵存储器中的符号数据进行寻址和输出。 FIFO存储器可以包含至少234个存储单元。

公开(公告)号：US07684448B2

公开(公告)日：2010-03-23

申请号：US11626896

申请日：2007-01-25

申请人： Huajia Li

发明人： Huajia Li

IPC分类号： H04J3/04

CPC分类号： H04L1/0071 ,  H03M13/2714 ,  H03M13/2742 ,  H04B1/7103 ,  H04B2201/709709

摘要： A method for data interleaving and data de-interleaving against periodical position interference, the process of data interleaving includes: multiplexing data of different transport channels, interleaving the data multiplexed, and outputting the data interleaved; the process of data de-interleaving includes: receiving the data interleaved, de-interleaving the data received, and de-multiplexing the data de-interleaved into different transport channels; performing a randomized operation in the process of the data interleaving and an inverse operation of the randomized calculation in the process of the data de-interleaving to make the outputted position of the data of different transport channels after the interleaving be random. It may be avoided by applying the present invention that all synchronization interference signals in a wireless channel are concentrated in the data of the same transport channel.

摘要翻译： 一种针对周期性位置干扰的数据交织和数据解交织的方法，数据交织处理包括：复用不同传输信道的数据，交织多路复用数据，并输出交织的数据; 数据解交织的过程包括：接收数据交织，解交织接收的数据，并将解交织的数据解复用为不同的传输信道; 在数据解交织处理中进行数据交织处理中的随机化操作和随机化计算的反向操作，以使交织后的不同传输信道的数据的输出位置是随机的。 通过应用本发明可以避免无线信道中的所有同步干扰信号集中在相同传输信道的数据中。

公开(公告)号：US20070101231A1

公开(公告)日：2007-05-03

申请号：US10596369

申请日：2004-12-08

申请人： Gideon Kutz ,  Amir Chass

发明人： Gideon Kutz ,  Amir Chass

IPC分类号： H03M13/00

CPC分类号： H03M13/6519 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/276 ,  H03M13/2767 ,  H03M13/2771

摘要： An interleaver for a turbo encoder and decoder comprising a first table populated with a first set of parameters to allow intra-row permutation of data within an array in accordance with a first wireless communication standard when operation in the first wireless communication standard is required and a second table populated with a second set of parameters to allow inter-row permutation of the data in accordance with the first wireless communication standard when operation in the first wireless communication standard is required wherein the first table is populated with a third set of parameters to allow intra-row permutation of data within an array in accordance with a second wireless communication standard when operation in the second wireless communication standard is required and to populate the second table with a fourth set of parameters to allow inter-row permutation of the data in accordance with the second wireless communication standard when operation in the second wireless communication standard is required.

摘要翻译： 一种用于turbo编码器和解码器的交织器，包括填充有第一组参数的第一表，以便在需要第一无线通信标准中的操作时根据第一无线通信标准允许阵列内的数据的行内置换，并且 第二表填充有第二组参数，以在需要在第一无线通信标准中进行操作时允许根据第一无线通信标准的数据的行间排列，其中第一表填充第三组参数以允许 当需要第二无线通信标准中的操作时，根据第二无线通信标准在阵列内的数据的行内置换，并且用第四组参数填充第二表，以允许根据数据的行间排列 具有第二无线通信标准，当在第二无线操作时 通信标准是必需的。

公开(公告)号：US20060242476A1

公开(公告)日：2006-10-26

申请号：US11103489

申请日：2005-04-12

申请人： Mark Bickerstaff ,  Yi-Chen Li ,  Chris Nicol ,  Bejamin Widdup

发明人： Mark Bickerstaff ,  Yi-Chen Li ,  Chris Nicol ,  Bejamin Widdup

IPC分类号： G11C29/00

CPC分类号： H03M13/2775 ,  H03M13/2714 ,  H03M13/276 ,  H03M13/2771 ,  H03M13/6516 ,  H03M13/6519

摘要： An interleaver address generator is provided with pruning avoidance technology. It anticipates the points in time when incorrect addresses are computed by an IAG, and bypasses these events. It produces a stream of valid, contiguous addresses for all specified code block sizes. A single address computation engine firstly ‘trains’ itself about violating generated addresses (for a related block size) during the initial H1 half-iteration of decoder operation, and then produces a continuous, correct stream of addresses as required by the turbo decoder. Thus regions of pruned addresses are determined, and then training is performed only in these regions. Thus, computation and population of a pruned event table is determined in less than 1/10 the time required to do a conventional style full training. The resulting pruned event table is compressed down to 256 bits.

摘要翻译： 交织器地址发生器具有修剪避免技术。 它预计在IAG计算不正确地址的时间点，并绕过这些事件。 它为所有指定的代码块大小生成一个有效，连续的地址流。 单个地址计算引擎首先在解码器操作的初始H1半迭代期间“违反”生成的地址（对于相关块大小）进行“训练”，然后根据turbo解码器的要求产生连续的正确的地址流。 因此，确定了修剪地址的区域，然后仅在这些区域中执行训练。 因此，修剪事件表的计算和人口在不到传统风格完全训练所需时间的1/10内确定。 生成的修剪事件表被压缩到256位。

公开(公告)号：US07091889B2

公开(公告)日：2006-08-15

申请号：US10526519

申请日：2002-09-09

申请人： Ralf Kukla ,  Stefan Schütz ,  Georg Spörlein ,  Gerd Mörsberger

发明人： Ralf Kukla ,  Stefan Schütz ,  Georg Spörlein ,  Gerd Mörsberger

IPC分类号： H03M7/00

CPC分类号： H04L1/0071 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/635

摘要： This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting. according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the interleaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.

摘要翻译： 本发明涉及一种用于根据交织方案将包含K个比特的输入序列交织到交错序列中的方法，包括以下步骤：（a）将输入序列存储在第一存储器装置中，（b）产生第一索引 交错序列的N个后续位，其中1 m（F）N m（F）K，（c）转换。 根据所述交织方案的逆，所述第一索引为指示所述交错序列的所述N个后续位存储在所述第一存储器装置中的位置的第二索引，以及（d）从所述第一存储器装置中的所述位置读出所述N个后续位 所述第一存储器装置，从而产生所述交错序列的至少一部分。

公开(公告)号：US20050248473A1

公开(公告)日：2005-11-10

申请号：US10526519

申请日：2002-09-09

申请人： Ralf Kukla ,  Stefan Schutz ,  Georg Sporlein ,  Gerd Morsberger

发明人： Ralf Kukla ,  Stefan Schutz ,  Georg Sporlein ,  Gerd Morsberger

IPC分类号： H03M13/27 ,  H03M13/29 ,  H04L1/00 ,  H03M7/00

CPC分类号： H04L1/0071 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/635

摘要： This invention relates to a method for interleaving, according to an interleaving scheme, an input sequence comprising K bits into an interleaved sequence, comprising the steps of (a) storing the input sequence in a first memory means, (b) generating first indices of N succeeding bits of the interleaved sequence, wherein 1 m(F) N m(F) K, (c) converting, according to an inverse of said interleaving scheme, said first indices into second indices indicative of the positions where said N succeeding bits of the inter-leaved sequence are stored in said first memory means, and (d) reading out said N succeeding bits from said positions in said first memory means, thereby generating at least part of said interleaved sequence.

摘要翻译： 本发明涉及一种根据交织方案将包括K个比特的输入序列交织到交错序列中的方法，包括以下步骤：（a）将输入序列存储在第一存储器装置中，（b）产生第一索引 其中1 m（F）N m（F）K，（c）根据所述交织方案的反向将所述第一索引转换为指示所述N个后续比特的位置的第二索引 并且（d）从所述第一存储器装置中的所述位置读出所述N个后续位，从而产生所述交错序列的至少一部分。

公开(公告)号：US20050234862A1

公开(公告)日：2005-10-20

申请号：US11103932

申请日：2005-04-12

申请人： Ying-Heng Shih

发明人： Ying-Heng Shih

IPC分类号： G06F7/00 ,  H03M13/27 ,  H04L1/00

CPC分类号： H04L1/0041 ,  H03M13/2714 ,  H03M13/2764 ,  H03M13/2771 ,  H04L1/0066 ,  H04L1/0071

摘要： A method, adapted to a 3GPP turbo coder, for interleaving a plurality of data of a data frame and a circuit thereof is provided. The present invention computes a value of Row Parameter according to the size of the data frame, computes an index for a table according to the value of Row Parameter, and searches for a value of Column Parameter, a value of Prime Parameter and a value of Primitive Parameter from the table.

摘要翻译： 提供一种适用于3GPP turbo编码器的用于交织数据帧的多个数据及其电路的方法。 本发明根据数据帧的大小计算行参数的值，根据Row Parameter的值计算表的索引，并搜索Column Parameter的值，Prime参数的值和 原始参数从表中。

公开(公告)号：US20050160347A1

公开(公告)日：2005-07-21

申请号：US11038183

申请日：2005-01-21

申请人： Min-Goo Kim ,  Sang-Hyuck Ha ,  Young-Mo Gu

发明人： Min-Goo Kim ,  Sang-Hyuck Ha ,  Young-Mo Gu

IPC分类号： H03M13/37 ,  H03M13/03 ,  H04L1/00 ,  H04L5/02 ,  H04L25/497

CPC分类号： H04L1/0066 ,  H03M13/271 ,  H03M13/2714 ,  H03M13/2957 ,  H03M13/6356 ,  H03M13/6362 ,  H04L1/0068 ,  H04L5/023 ,  H04L25/497

摘要： An apparatus for generating Quasi-Complementary Duo-Binary Turbo Codes (QC-DBTC). The apparatus includes a QC-DBTC encoder which receives an information symbol stream and generates a plurality of systematic symbol streams and a plurality of parity symbol streams according to a given code rate. The apparatus further includes a quad-symbol mapper which quad-maps the systematic symbol streams to one symbol stream, a channel interleaver which independently interleaves the quad-mapped systematic symbol stream and the parity symbol streams, quad-demaps the quad-mapped systematic symbol stream, interlaces symbols in parity symbol streams, and serial-concatenates the quad-demapped systematic symbol stream to the interlaced parity symbol streams. A duo-binary turbo code generator is further provided to repeat the serial-concatenated symbol stream, and select a predetermined number of symbols from the repeated symbol stream according to a code rate and selection information, thereby generating QC-DBTC codes.

摘要翻译： 一种用于产生准互补二进制Turbo码（QC-DBTC）的装置。 该装置包括QC-DBTC编码器，其接收信息符号流，并根据给定的码率产生多个系统符号流和多个奇偶校验符号流。 该装置还包括将系统符号流四维映射到一个符号流的四符号映射器，独立地交错四映射系统符号流和奇偶校验符号流的信道交织器，将四映射系统符号 流，在奇偶校验符号流中交织符号，并将四次映射映射的系统符号流串行连接到隔行扫描奇偶校验符号流。 进一步提供二进制二进制turbo码发生器以重复串联连接的符号流，并根据码率和选择信息从重复符号流中选择预定数量的码元，由此产生QC-DBTC码。