公开(公告)号：US2352956A

公开(公告)日：1944-07-04

申请号：US37471241

申请日：1941-01-16

Applicant: OTTO STRUTT MAXIMILIAAN JULIUS ,  DER ZIEL ALDERT VAN ,  JAN BAKKER CORNELIS

Inventor： OTTO STRUTT MAXIMILIAAN JULIUS ,  DER ZIEL ALDERT VAN ,  JAN BAKKER CORNELIS

IPC: H01J19/82 ,  H01J25/10 ,  H01J25/12 ,  H01J43/02 ,  H03D7/00 ,  H03D7/10 ,  H03F1/08 ,  H03F1/28 ,  H03F1/36 ,  H03F3/52 ,  H03G3/22 ,  H03G5/06 ,  H03J3/06 ,  H04B15/06

CPC classification number: H01J25/10 ,  H01J19/82 ,  H01J25/12 ,  H01J43/025 ,  H03D7/00 ,  H03D7/10 ,  H03F1/08 ,  H03F1/28 ,  H03F1/36 ,  H03F3/52 ,  H03G3/22 ,  H03G5/06 ,  H03J3/06 ,  H04B15/06

公开(公告)号：US2111702A

公开(公告)日：1938-03-22

申请号：US9079036

申请日：1936-07-15

Applicant: PHILIPS NV

Inventor： OTTO STRUTT MAXIMILIAAN JULIUS

IPC: H01J19/82 ,  H03F1/08 ,  H03F1/16

CPC classification number: H01J19/82 ,  H03F1/08 ,  H03F1/16

公开(公告)号：US1971447A

公开(公告)日：1934-08-28

申请号：US43601030

申请日：1930-03-15

Applicant: RCA CORP

Inventor： JAN GROENEVELD YME BOUWINUS FO ,  EKKO OOSTERHUIS

IPC: H01J19/66 ,  H01J19/82

CPC classification number: H01J19/82

公开(公告)号：US10903034B2

公开(公告)日：2021-01-26

申请号：US16342475

申请日：2017-10-17

Applicant: WiSys Technology Foundation, Inc.

Inventor： Charles D Nelson ,  Harold T Evensen

IPC: H01J21/10 ,  H01J9/02 ,  H01J19/24 ,  H01J19/38 ,  H01L51/00 ,  H01L51/05 ,  H01J1/304 ,  H01J19/82 ,  H01J9/18 ,  H01L51/10

Abstract: A field emission transistor uses carbon nanotubes positioned to extend along a substrate plane rather than perpendicularly thereto. The carbon nanotubes may be pre-manufactured and applied to the substrate and then may be etched to create a gap between the carbon nanotubes and an anode through which electrons may flow by field emission. A planar gate may be positioned beneath the gap to provide a triode structure.

公开(公告)号：US07994842B2

公开(公告)日：2011-08-09

申请号：US12482044

申请日：2009-06-10

Applicant: Minoru Ito

Inventor： Minoru Ito

IPC: H01J19/82 ,  H02M7/00

CPC classification number: H03K19/00384

Abstract: Semiconductor integrated circuit apparatus and electronic apparatus having a leakage current detection circuit where arbitrarily set leakage current detection ratio does not depend on power supply voltage, temperature, or manufacturing variations, and where leakage current detection is straightforward. Semiconductor integrated circuit apparatus extracts a stable potential from the center of two NchMIS transistors, amplifies drain current of an NchMOS transistor taking this potential as a gate potential to a current value of an arbitrary ratio using current mirror circuit, makes this current value flow through NchMOS transistor with the gate and drain connected, and applies drain potential of this NchMOS transistor to the gate of leakage current detection NchMOS transistor.

Abstract translation: 具有泄漏电流检测电路的半导体集成电路装置和电子设备，其中任意设置的漏电流检测率不依赖于电源电压，温度或制造变化，并且其中泄漏电流检测是直接的。 半导体集成电路装置从两个NchMIS晶体管的中心提取稳定电位，使用电流镜电路将NchMOS晶体管的漏极电流放大到任意比例的电流值，使该电位作为栅极电位，使该电流值流过NchMOS 晶体管与栅极和漏极连接，并将NchMOS晶体管的漏极电压施加到漏电流检测NchMOS晶体管的栅极。

公开(公告)号：US07944273B1

公开(公告)日：2011-05-17

申请号：US12143364

申请日：2008-06-20

Applicant: Patrizio Vinciarelli ,  Michael Briere ,  Jeffrey Gordon Dumas

Inventor： Patrizio Vinciarelli ,  Michael Briere ,  Jeffrey Gordon Dumas

IPC: H01J19/82

CPC classification number: H02M1/32

Abstract: Techniques for adjusting the voltage across an active filter element include a controlled circuit element and a control circuit element adapted to control the voltage across the controlled circuit element to increase transient load response and to reduce power dissipation.

Abstract translation: 用于调整有源滤波器元件两端的电压的技术包括受控电路元件和控制电路元件，其适于控制跨受控电路元件的电压以增加瞬态负载响应并降低功耗。

公开(公告)号：US07616050B2

公开(公告)日：2009-11-10

申请号：US11302228

申请日：2005-12-14

Applicant: Wolfgang Eckstein

Inventor： Wolfgang Eckstein

IPC: H01J19/82

CPC classification number: G05F1/465

Abstract: A power supply circuit is provided for producing a reference current with a prescribable temperature dependence. The circuit includes two current sinks, which at their respective input take up a first input current (I1) or a second input current (I2), and in which current sinks at their respective outputs are connected to a node having a reference potential, the output of at least one current sink being connected via a resistor to the node having the reference potential. The resistor is formed by least two reference resistors with prescribable temperature coefficients that are preferably different from one another.

Abstract translation: 提供电源电路用于产生具有规定温度依赖性的参考电流。 该电路包括两个电流吸收器，它们在它们各自的输入处占据第一输入电流（I1）或第二输入电流（I2），并且其中在其相应输出端的电流吸收连接到具有参考电位的节点， 至少一个电流吸收器的输出经由电阻器连接到具有参考电位的节点。 电阻器由至少两个参考电阻器形成，其具有规定的温度系数，其优选地彼此不同。

公开(公告)号：US07532017B2

公开(公告)日：2009-05-12

申请号：US11865977

申请日：2007-10-02

Applicant: Douglas Paul Anderson

Inventor： Douglas Paul Anderson

IPC: G01R27/08 ,  G06F1/00 ,  H01J19/82

CPC classification number: G01R27/16 ,  H04L12/10

Abstract: An AC maintain power signature detection circuit in a power sourcing equipment (PSE) for a Power over Ethernet system injects an AC test signal onto a power port of the PSE. The AC test signal is driven onto a first power terminal of the power port through a sense resistor. The voltages across the sense resistor are measured and scaled by first and second resistor dividers having different resistor ratios. The voltage and the scaled voltage at the first power terminal side of the sense resistor have a peak voltage being proportional to the load impedance of the load coupled to the power port. The comparator compares the scaled voltages measured across the sense resistor and generates the output signal indicative of the load impedance at the power port.

Abstract translation: 用于以太网供电系统的电源设备（PSE）中的AC维护功率签名检测电路将AC测试信号注入到PSE的电源端口。 交流测试信号通过检测电阻驱动到电源端口的第一个电源端子上。 检测电阻两端的电压由具有不同电阻比的第一和第二电阻分压器测量和缩放。 检测电阻器的第一电源端侧的电压和标定电压具有与耦合到电源端口的负载的负载阻抗成比例的峰值电压。 比较器比较在感测电阻器上测量的定标电压，并产生指示电源端口处的负载阻抗的输出信号。

公开(公告)号：US07102420B2

公开(公告)日：2006-09-05

申请号：US10316360

申请日：2002-12-11

Applicant: Hiroaki Uchida

Inventor： Hiroaki Uchida

IPC: H01J19/82

CPC classification number: H01L28/84 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76895 ,  H01L27/10852 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some of the members constituting a semiconductor element are formed from α-Si and an HSG forming process is implemented to form hemispherical polysilicon grains at some of the members formed from α-Si. Thus, a semiconductor device that is achieved without requiring a great number of manufacturing steps such as film formation and etching, facilitates control of the individual steps and assures reliable electrical connection between the members and a method of manufacturing such a semiconductor device are provided.

公开(公告)号：US07023264B2

公开(公告)日：2006-04-04

申请号：US10500858

申请日：2003-01-22

Applicant: Yoshihiko Horio ,  Tetsuya Fujiwara ,  Kazuyuki Aihara

Inventor： Yoshihiko Horio ,  Tetsuya Fujiwara ,  Kazuyuki Aihara

IPC: H01J19/82

CPC classification number: H03H11/53 ,  H03H11/52

Abstract: An N-shaped nonlinear resistor circuit using floating gate MOSFETs; to realize various N-shaped characteristics that can be approximated by piecewise linear functions of third to seventh orders and further to realize N-shaped V-I characteristics that can variously change those characteristics by use of external voltages. A Λ-type nonlinear resistor circuit (1) and a V-type nonlinear resistor circuit (2) using multi-input floating gate MOSFETs are connected in parallel, and the currents of the Λ-type and V-type nonlinear resistor circuits are added together, thereby providing various N-shaped voltage-current characteristics.

Abstract translation: 使用浮栅的N形非线性电阻电路; 以实现可以通过第三到第七阶的分段线性函数近似的各种N形特性，并且还实现可以通过使用外部电压来各种改变这些特性的N形V-I特性。 使用多输入浮栅MOSFET的Lambda型非线性电阻电路（1）和V型非线性电阻电路（2）并联连接，并且增加了L型和V型非线性电阻电路的电流 从而提供各种N形电压 - 电流特性。