Adaptive ARQ feedback bandwidth allocation
    51.
    发明授权
    Adaptive ARQ feedback bandwidth allocation 有权
    自适应ARQ反馈带宽分配

    公开(公告)号:US06505034B1

    公开(公告)日:2003-01-07

    申请号:US09466852

    申请日:1999-12-20

    申请人: Armin Wellig

    发明人: Armin Wellig

    IPC分类号: H03M1300

    摘要: A ARQ actions taken in the data link layer control (DLC) in a wireless communications system for data transmission is implemented by using the HiperLAN/2 protocol that has a selective retransmission process to complete bitmaps when there are errors in data unit transmissions. More particularly it pertains to adaptive allocation of ARQ feedback bandwidth to economize on the use of bandwidth. This is achieved by informing the scheduler of the status of received and non-received data units at the receiver to allow adaptive ARQ feedback bandwidth during data transmission. The information about the status of data units at the receiver is provided by the ABIR flag contained in the ARQ feedback message. If there are many unacknowledged messages of,data units, the ABIR flag is set and the scheduler increases bandwidth to accommodate the traffic of retransmitted messages that were omitted. When the situation has returned to normal, that is, there are minimal messages waiting to be retransmitted the ABIR flag is set to null and no added bandwidth is assigned. This technique can be used also to find the lowest level of bandwidth by decreasing bandwidth until there is a backup in traffic of retransmissions and increasing bandwidth at that time.

    摘要翻译: 在用于数据传输的无线通信系统中的数据链路层控制(DLC)中采取的ARQ动作通过使用具有选择性重传过程的HiperLAN / 2协议来实现,当在数据单元传输中存在错误时完成位图。 更具体地说,它涉及ARQ反馈带宽的自适应分配以节省带宽的使用。 这通过在接收机处通知调度器接收到的和未接收的数据单元的状态来实现,以便在数据传输期间允许自适应ARQ反馈带宽。 接收机上数据单元状态的信息由ARQ反馈消息中包含的ABIR标志提供。 如果存在许多未确认的数据单元的消息,则设置ABIR标志,并且调度器增加带宽以适应被省略的重传消息的业务。 当情况恢复正常时,也就是说,等待重发的消息最少,ABIR标志设置为null,没有分配带宽。 这种技术还可以用于通过减少带宽来找到最低级别的带宽,直到在传输流量的备份和当时的带宽增加。

    Method and apparatus for randomizing sector addresses in a disk storage device
    52.
    发明授权
    Method and apparatus for randomizing sector addresses in a disk storage device 失效
    用于随机化盘存储装置中的扇区地址的方法和装置

    公开(公告)号:US06502217B1

    公开(公告)日:2002-12-31

    申请号:US09361628

    申请日:1999-07-27

    申请人: Kazushi Shimizu

    发明人: Kazushi Shimizu

    IPC分类号: H03M1300

    CPC分类号: G11B20/10 G11B20/18

    摘要: Disclosed herein is a disk drive in which servo-sector addresses are reproduced from a disk, a target data sector to be accessed is specified, and data is read from or written in the target data sector. The servo-sector addresses are recorded on the disk and randomized in accordance with a specific translation rule, thus arranged in an order different from the order they should be arranged in the same cylinder. The disk drive has a read head and a CPU. The head reads the randomized servo-sector addresses from the disk. The CPU refers to a back translation table, translating the servo-sector addresses back to the original servo-sector addresses. The CPU then checks the continuity of each servo-sector address with respect to the adjacent ones. If the servo-sector address has have no continuity, the CPU determines that the servo-sector address has an error.

    摘要翻译: 这里公开了一种磁盘驱动器,其中从盘再现伺服扇区地址,指定要访问的目标数据扇区,并且从目标数据扇区读取或写入数据。 伺服扇区地址被记录在磁盘上并根据特定的转换规则随机化,因此按与它们应该排列在相同气缸中的顺序不同的顺序排列。 磁盘驱动器具有读取头和CPU。 头从磁盘读取随机的伺服扇区地址。 CPU是指一个反向转换表,将伺服扇区地址转换回原始的伺服扇区地址。 然后,CPU检查每个伺服扇区地址相对于相邻的地址的连续性。 如果伺服扇区地址没有连续性,则CPU确定伺服扇区地址有错误。

    Iterated soft-decision decoding of block codes
    53.
    发明授权
    Iterated soft-decision decoding of block codes 有权
    块代码的迭代软判决解码

    公开(公告)号:US06499128B1

    公开(公告)日:2002-12-24

    申请号:US09253146

    申请日:1999-02-18

    IPC分类号: H03M1300

    摘要: Systems and methods for augmenting the performance of iterative soft decision-in soft decision-out decoding of block codes with extrinsic information based on multiple parity equations inherent to the block codes. Cyclic shifting of codewords may be applied in the context of iterative soft decision-in soft decision-out decoding to maximize the usefulness of a parity equation corresponding to any particular codeword bit. Soft decisions are determined on a bit-by-bit basis in response to multi-bit symbol measurements. This allows the use of relatively inexpensive bit-based decoders for decoding of multi-bit symbols.

    摘要翻译: 基于块代码固有的多重奇偶校验方法,增加具有外部信息的块代码的迭代软判决软判决解码性能的系统和方法。 可以在迭代软判决软判决解码的上下文中应用码字的循环移位,以最大化对应于任何特定码字比特的奇偶校验方程的有用性。 响应于多位符号测量,逐位确定软判决。 这允许使用相对便宜的基于比特的解码器来解码多位符号。

    Reed-solomon decoder
    54.
    发明授权
    Reed-solomon decoder 失效
    里德独奏解码器

    公开(公告)号:US06487691B1

    公开(公告)日:2002-11-26

    申请号:US09401051

    申请日:1999-09-22

    IPC分类号: H03M1300

    摘要: A Reed-Solomon decoder that can correct t errors or fewer which includes: a syndrome calculation circuit for calculating syndromes Sj (J=0, 1, . . . , 2t−1) using the first codeword Yi (i=0, 1, . . . , n−1) (so-called received codeword) that may include errors; and a coefficient calculation circuit for, by using the syndromes Sj, calculating coefficients &Lgr;k (k=1, . . . , e) of an error-locator polynomial. The coefficients &Lgr;k correspond in number to e estimated errors (e≦t

    摘要翻译: 可以校正t误差或更少的Reed-Solomon解码器,其包括:使用第一码字Yi(i = 0,1,...)来计算综合征Sj(J = 0,1,...,2t-1)的校正子计算电路, ...,n-1)(所谓的接收码字),可能包括错误; 以及用于通过使用校正子Sj的误差定位多项式的计算系数LAMBDk(k = 1,...,e)的系数计算电路。 系数LAMBDk在数量上对应于估计的误差(e <= t

    Arrangements and method relating to transmission of digital data
    55.
    发明授权
    Arrangements and method relating to transmission of digital data 有权
    与数字数据传输相关的安排和方法

    公开(公告)号:US06470472B1

    公开(公告)日:2002-10-22

    申请号:US09426105

    申请日:1999-10-22

    申请人: Magnus Johansson

    发明人: Magnus Johansson

    IPC分类号: H03M1300

    CPC分类号: H03M13/091

    摘要: A receiving arrangement receives digitally coded data signals transported over a channel. The data signal includes sequences divided into blocks, and the receiving arrangement includes an error correcting device providing a number of alternative blocks, an error detecting device, and a storing device for storing information relating to each possible block position of a sequence. The error detecting device includes a differential CRC-decoder including a first decoding device for decoding a sequence of blocks using a reference sequence to provide a reference syndrome and a second decoding device for decoding selected alternative differential blocks of the sequence obtainable via the error correcting device. The differential blocks are calculated as a difference between the corresponding block of the reference sequence and alternative blocks, respectively, to provide differential syndromes. The resulting syndromes are calculated as a sum of the reference syndrome and of a number of differential syndromes, respectively.

    摘要翻译: 接收装置接收通过信道传输的数字编码的数据信号。 数据信号包括分成块的序列,并且接收装置包括提供多个替代块的纠错装置,错误检测装置和用于存储与序列的每个可能的块位置有关的信息的存储装置。 误差检测装置包括差分CRC解码器,该差分CRC解码器包括第一解码装置,用于使用参考序列解码块序列以提供参考综合征;以及第二解码装置,用于解码通过纠错装置可获得的序列的选定备选差分块 。 差分块被分别计算为参考序列和替代块的相应块之间的差,以提供差异综合征。 所得到的综合征分别计算为参考综合征和多个差异综合征的总和。

    Error correcting device and optical disk reader comprising same
    57.
    发明授权
    Error correcting device and optical disk reader comprising same 有权
    误差校正装置和包括其的光盘读取器

    公开(公告)号:US06453441B1

    公开(公告)日:2002-09-17

    申请号:US09646053

    申请日:2001-02-08

    IPC分类号: H03M1300

    摘要: A compact and fast coder-decoder of the Reed-Solomon type and a reader, which comprises such a coder-decoder. The present invention provides a coder-decoder that includes specific registers that are divided into elementary cells set in series and comprising means of multiplexing and of calculation such that during a cycle of a clock signal the data of two of the registers are shifted from one cell and a calculation operation is carried out for one of the data and it is subsequently possible to exchange simultaneously the data between the two registers.

    摘要翻译: Reed-Solomon类型的紧凑且快速的编码器解码器和包括这样的编码器解码器的读取器。 本发明提供了一种编码器解码器,其包括被划分成串联设置的基本单元的特定寄存器,并且包括复用和计算装置,使得在时钟信号的周期期间,两个寄存器的数据从一个单元 并且对于数据之一执行计算操作,并且随后可以同时交换两个寄存器之间的数据。

    Pseudo product code encoding and decoding apparatus and method
    58.
    发明授权
    Pseudo product code encoding and decoding apparatus and method 失效
    伪产品编码解码装置及方法

    公开(公告)号:US06453439B1

    公开(公告)日:2002-09-17

    申请号:US09501613

    申请日:2000-02-10

    IPC分类号: H03M1300

    CPC分类号: H03M13/2906 H03M13/27

    摘要: A pseudo product code decoder effects error correction by using parity symbols of a first linear-structure error correction code contained in an input symbol train that constitutes a pseudo product code and by using parity symbols of a second linear-structure error correction code. Second-series information symbols are extracted from the symbol train; and a subtraction code of a pseudo product code codeword is formed of the second-series information symbols, with the first-series information symbol portion and the second linear-structure error correction code portion being changed to zero codes. The pseudo product code codeword is transformed into a product code codeword by subtracting processing with the subtraction code. Decoding processing is performed a plurality of times on the symbol train of the product code codeword, thereby effecting error correction; and first-series information symbols are extracted from the error corrected symbol train.

    摘要翻译: 伪产品代码解码器通过使用包含在构成伪乘积代码的输入符号串中的第一线性结构错误校正码的奇偶校验符号并且通过使用第二线性结构错误校正码的奇偶校验符号来实现纠错。 从符号列中提取第二序列信息符号; 并且第一系列信息符号部分和第二线性结构纠错码部分被改变为零代码,由第二系列信息符号形成伪乘积码字的减法码。 通过用减法代码减去处理,将伪乘积代码码变换为乘积代码字。 在乘积代码字的符号列上执行多次解码处理,从而进行纠错; 并且从错误校正的符号列中提取第一系列信息符号。

    Flexible method of error protection in communications systems
    59.
    发明授权
    Flexible method of error protection in communications systems 有权
    通信系统中灵活的错误保护方法

    公开(公告)号:US06405340B1

    公开(公告)日:2002-06-11

    申请号:US09347251

    申请日:1999-07-02

    IPC分类号: H03M1300

    摘要: A flexible method of error coding uses at least two generating polynomials to provide different degrees of error protection and to optionally superimpose a phantom channel on a primary channel, without the need for explicit signaling from transmitter to receiver. An encoded message is CRC decoded on the receive side with at least two different generating polynomials. Based on the results of the twin decoding, the present method can determine which of the generating polynomials was used to encode the message and respond accordingly. For instance, if a particular generating polynomial was used, then this may indicate that a second channel has been superimposed onto the primary channel and that second channel may be extracted. On the other hand, if another generating polynomial, such as the default generating polynomial, was used, this may be used to indicate that no second channel has been superimposed. In some embodiments, the method may optionally be refined by adding additional steps to resolve potential ambiguities resulting from the use of a twin decoding scheme. In essence, the receiver deduces the transmitter's choice of CRC generating code, and thus the degree of redundancy and/or presence of the second channel, by analyzing the incoming bit stream rather than relying on explicit signaling information and, armed with that knowledge, responds accordingly.

    摘要翻译: 灵活的错误编码方法使用至少两个生成多项式来提供不同程度的错误保护,并且可选地在主信道上叠加幻像通道,而不需要从发射机到接收机的显式信令。 编码消息在接收侧被CRC解码,具有至少两个不同的生成多项式。 基于双解码的结果,本方法可以确定哪个生成多项式用于对消息进行编码并相应地进行响应。 例如,如果使用特定的生成多项式,则这可以指示第二信道已经叠加到主信道上,并且可以提取第二信道。 另一方面,如果使用诸如默认生成多项式的另一生成多项式,则这可以用于指示没有叠加第二通道。 在一些实施例中,可以可选地通过添加附加步骤来解决由使用双解码方案导致的潜在模糊性来改进该方法。 实质上,接收机通过分析传入比特流而不是依赖于明确的信令信息来推导发射机对CRC生成代码的选择,从而减少第二信道的冗余度和/或存在的程度,并且根据该知识来响应 相应地。

    Normalization implementation for a logmap decoder
    60.
    发明授权
    Normalization implementation for a logmap decoder 有权
    日志对照解码器的规范化实现

    公开(公告)号:US06400290B1

    公开(公告)日:2002-06-04

    申请号:US09511206

    申请日:2000-02-23

    IPC分类号: H03M1300

    CPC分类号: H03M13/3905 H03M13/6583

    摘要: A programmable logic device can be programmed to configure its logic elements to approximate the normalization of probability values used in the operation of logMAP decoders, thereby significantly reducing the amount of logic resources required in the normalization procedure without significantly degrading performance. In the first preferred embodiment, normalization is achieved by approximating the normalization value by calculating an approximate normalization value which is then deducted from all &agr; values in the trellis at any time. This is done by logically ANDing all &agr; input probability values with the NOT of their own MSBs. The resulting outputs are then all bitwise ORed together, the output of which is the approximate normalization value. In another embodiment, the approximate normalization value is calculated using a fixed constant determinable at the outset of the logMAP decoder operation.

    摘要翻译: 可编程逻辑器件可以配置其逻辑元件来近似在logMAP解码器的操作中使用的概率值的归一化,从而显着减少归一化过程中所需的逻辑资源量,而不会显着降低性能。 在第一优选实施例中,通过近似归一化值来实现归一化,即通过计算随后从网格中的所有α值中扣除的近似归一化值。 这是通过将所有alpha输入概率值与其自己的MSB的NOT进行逻辑与运算来完成的。 所得到的输出随后全部按位或相加在一起,其输出是近似归一化值。 在另一个实施例中,使用在logMAP解码器操作开始时可确定的固定常数来计算近似归一化值。