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    Gate all around vacuum channel transistor
    591.
    发明授权
    Gate all around vacuum channel transistor 有权

    公开(公告)号：US11031504B2

    公开(公告)日：2021-06-08

    申请号：US16878287

    申请日：2020-05-19

    Applicant: STMICROELECTRONICS, INC.

    Inventor： John H. Zhang

    IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01J21/10

    Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

    Human presence detection
    592.
    发明授权
    Human presence detection 有权

    公开(公告)号：US11030289B2

    公开(公告)日：2021-06-08

    申请号：US16050628

    申请日：2018-07-31

    Applicant: STMicroelectronics, Inc.

    Inventor： Xiaoyong Yang ,  Sankalp Dayal

    IPC: G06F21/32 ,  G01C3/08 ,  G01C19/58 ,  G10L17/00 ,  G01P15/16 ,  G06F21/31

    Abstract: A method includes sensing through time-of-flight measurements a distance of an object from an electronic device, sensing motion of the electronic device, sensing acoustic signals received by the electronic device, and detecting the presence of a human proximate the electronic device based on the sensed distance, motion and acoustic signals. Access to the electronic device is controlled based on whether a human is detected as being present.

    PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME
    595.
    发明申请
    PACKAGE WITH INTERLOCKING LEADS AND MANUFACTURING THE SAME 有权

    公开(公告)号：US20210118818A1

    公开(公告)日：2021-04-22

    申请号：US17137262

    申请日：2020-12-29

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Aaron Cadag ,  Lester Joseph Belalo ,  Ela Mia Cadag

    IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

    Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame. This differential in height reduces the span of wires used to form electrical connections within the semiconductor package. These reductions in the span of the wires reduces the chances of wire to wire and wire to die short circuiting because the wire sweep of the wires is reduced when the molding compound is placed.

    Control circuit for power switch
    599.
    发明授权
    Control circuit for power switch 有权

    公开(公告)号：US10917087B2

    公开(公告)日：2021-02-09

    申请号：US16719053

    申请日：2019-12-18

    Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS, INC ,  STMICROELECTRONICS (ALPS) SAS

    Inventor： Vanni Poletto ,  David F. Swanson ,  Giovanni Luca Torrisi ,  Laurent Chevalier

    IPC: H03K17/687 ,  G01R19/165 ,  G05B11/42 ,  G05F1/618 ,  G05F1/56 ,  H02J7/34

    Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.

    Atomic layer deposition of selected molecular clusters
    600.
    发明授权
    Atomic layer deposition of selected molecular clusters 有权

    公开(公告)号：US10892344B2

    公开(公告)日：2021-01-12

    申请号：US15981659

    申请日：2018-05-16

    Applicant: STMICROELECTRONICS, INC.

    Inventor： John H. Zhang

    IPC: H01L21/8238 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L29/45 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/285 ,  H01L21/768 ,  C23C14/04 ,  C23C14/22 ,  H01L29/66

    Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

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