公开(公告)号：US20060265570A1

公开(公告)日：2006-11-23

申请号：US11398857

申请日：2006-04-05

Applicant: Frederic Bancel ,  Nicolas Berard

Inventor： Frederic Bancel ,  Nicolas Berard

IPC: G06F15/00

CPC classification number: G06F11/28

Abstract: The present invention relates to a coprocessor comprising a calculation unit for executing a command, and a securisation device for monitoring the execution of the command and supplying an error signal having an active value as soon as the execution of the command begins and an inactive value at the end of the execution of the command, if no abnormal progress in the execution of the command has been detected. The coprocessor further comprises means for preventing access to at least one unit of the coprocessor, while the error signal is on the active value. Application is provided particularly but not exclusively to the protection of integrated circuits for smart cards against attacks by fault injection.

Abstract translation: 本发明涉及一种协处理器，其包括用于执行命令的计算单元和用于监视命令的执行的保护装置，并且一旦执行命令开始就提供具有活动值的错误信号， 执行命令的结束，如果没有检测到执行命令的异常进度。 协处理器还包括用于防止对协处理器的至少一个单元的访问的装置，同时误差信号处于活动值。 特别提供了应用，但不限于专门针对智能卡的集成电路来防止故障注入攻击。

公开(公告)号：US20060259839A1

公开(公告)日：2006-11-16

申请号：US11382602

申请日：2006-05-10

Applicant: Benoit Lasbouygues ,  Joel Schindler

Inventor： Benoit Lasbouygues ,  Joel Schindler

IPC: G01R31/28

CPC classification number: G06F17/5036

Abstract: The method evaluates a constraint of a sequential memory cell able to sample an input data item regulated by a clock signal. The constraint is dependent on the ramp of a first signal and on the ramp of a second signal. The method includes a characterization phase including a first step of determination in which a value of the second ramp is fixed, the value of the first ramp is made to vary so as to determine, a first set of values of the constraint. A second step of determination includes the value of the first ramp being fixed at one of its values taken during the first step of determination, the value of the second ramp is made to vary so as to determine for each value of the second ramp a deviation with respect to the value of the constraint belonging to the first set and corresponding to the fixed value of the first ramp. The method includes a third step of calculation in which the values of the constraint are calculated for all the values of the first ramp and of the second ramp, while adding the various deviations obtained to the values of the first set of values.

Abstract translation: 该方法评估能够对由时钟信号调节的输入数据项进行采样的顺序存储器单元的约束。 约束取决于第一信号的斜坡和第二信号的斜坡。 该方法包括表征阶段，包括确定第二斜坡的值是固定的第一步骤，第一斜坡的值被改变以确定约束的第一组值。 确定的第二步骤包括第一斜坡的值被固定在其在确定的第一步骤期间取得的其中一个值，第二斜坡的值被改变以便确定第二斜坡的每个值偏差 相对于属于第一组的约束的值对应于第一斜坡的固定值。 该方法包括第三计算步骤，其中针对第一斜坡和第二斜坡的所有值计算约束的值，同时将获得的各种偏差加到第一组值的值。

公开(公告)号：US20060233015A1

公开(公告)日：2006-10-19

申请号：US11394873

申请日：2006-03-31

Applicant: Jean-Pierre Schoellkopf

Inventor： Jean-Pierre Schoellkopf

IPC: G11C11/00

CPC classification number: G11C7/20 ,  G11C11/412 ,  Y10S257/901 ,  Y10S257/903

Abstract: A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS inverter is electrically insulated from the substrate of the NMOS transistor of the second CMOS inverter. The two substrates can be biased with the first voltage. A clear flash controller flash clears the cells for temporarily bring the bias of the substrate of the NMOS transistor of the first CMOS inverter to the second voltage.

Abstract translation: 静态存储器件包括具有两个交叉耦合CMOS反相器的至少一个存储单元，以连接到第一和第二电压。 第一CMOS反相器的NMOS晶体管的衬底与第二CMOS反相器的NMOS晶体管的衬底电绝缘。 两个基板可以用第一电压偏置。 清除闪光灯控制器闪光灯清除单元，以暂时将第一CMOS反相器的NMOS晶体管的衬底的偏置带到第二电压。

公开(公告)号：US07123092B2

公开(公告)日：2006-10-17

申请号：US10944679

申请日：2004-09-17

Applicant: Philippe Sirito-Olivier

Inventor： Philippe Sirito-Olivier

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F2203/45636

Abstract: A differential amplifier includes a pair of first and second transistors connected together. The first transistor includes a first conduction terminal, and a second conduction terminal forming a first output node of the amplifier. The second transistor includes a first conduction terminal connected to the first conduction terminal of the first transistor, and a second conduction terminal forming a second output node of the amplifier. A first inductive load is connected between the first output node and a supply reference, and a second inductive load is connected between the second output node and the supply reference. A limiting network limits output voltages on the first and second output nodes, and includes a first resistor connected to the first output node, and a second resistor connected to the second output node. The first and second resistors also connected together in series at a common intermediate node. A first analog switch is connected to the first resistor and to the supply reference, and a second analog switch connected to the second resistor and the supply reference via the first analog switch. The first and second analog switches are turned on when a voltage on the common intermediate node exceeds a threshold.

Abstract translation: 差分放大器包括连接在一起的一对第一和第二晶体管。 第一晶体管包括第一导电端子和形成放大器的第一输出节点的第二导电端子。 第二晶体管包括连接到第一晶体管的第一导通端子的第一导电端子和形成放大器的第二输出节点的第二导电端子。 第一感性负载连接在第一输出节点和供电基准之间，第二电感负载连接在第二输出节点和供电基准之间。 限制网络限制第一和第二输出节点上的输出电压，并且包括连接到第一输出节点的第一电阻器和连接到第二输出节点的第二电阻器。 第一和第二电阻器也在公共中间节点串联连接在一起。 第一模拟开关连接到第一电阻器和电源基准，以及通过第一模拟开关连接到第二电阻器和电源基准的第二模拟开关。 当公共中间节点上的电压超过阈值时，第一和第二模拟开关导通。

公开(公告)号：US20060219943A1

公开(公告)日：2006-10-05

申请号：US11392130

申请日：2006-03-29

Applicant: Siaudeau Jean-Louis

Inventor： Siaudeau Jean-Louis

IPC: G01N23/00

CPC classification number: H01L21/681 ,  H01L21/67259 ,  H01L21/67282 ,  H01L21/68 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and a system of alignment of an integrated circuit chip pick-and-place equipment with an origin of a wafer supporting these circuits, comprising optically searching on the wafer at least one reference pattern formed, on manufacturing of the integrated circuits, in a reference chip, the reference pattern being different from optically-recognizable patterns of the other chips.

公开(公告)号：US07106808B2

公开(公告)日：2006-09-12

申请号：US09827306

申请日：2001-04-05

Applicant: Pierre Busson ,  Pierre-Olivier Jouffre ,  Frédéric Paillardet

Inventor： Pierre Busson ,  Pierre-Olivier Jouffre ,  Frédéric Paillardet

IPC: H03K9/00

CPC classification number: H03G3/3068 ,  H03G3/3089

Abstract: A tuner includes an analog block, a digital block, and an analog/digital conversion stage connected therebetween. The analog block includes a first attenuator/controlled-gain amplifier stage connected upstream to a frequency transposition stage. The overall mean power of the entire signal received by the tuner is calculated during a phase of initialization. This overall calculated power is compared in the digital block with a first predetermined reference value corresponding to a maximum power desired at a predetermined location of the analog block. The gain of the first attenuator/amplifier stage is adjusted to minimize the deviation between the overall calculated power and the reference value. In a phase of normal operation, one of the channels of the signal received is selected, with the gain of the first attenuator/amplifier stage being fixed.

Abstract translation: 调谐器包括模拟块，数字块和连接在它们之间的模拟/数字转换级。 模拟模块包括连接到频率转置级上游的第一衰减器/受控增益放大器级。 在初始化阶段计算由调谐器接收的整个信号的总平均功率。 该总计算功率在数字模块中与对应于模拟模块的预定位置所需的最大功率的第一预定参考值进行比较。 调整第一衰减器/放大器级的增益以最小化总计算功率与参考值之间的偏差。 在正常操作的相位中，选择所接收的信号中的一个通道，其中第一衰减器/放大器级的增益是固定的。

公开(公告)号：US07102383B2

公开(公告)日：2006-09-05

申请号：US10480577

申请日：2002-06-12

Applicant: Andre Roger ,  Charles Aubenas ,  Julien Fabregues

Inventor： Andre Roger ,  Charles Aubenas ,  Julien Fabregues

IPC: H03K19/177

CPC classification number: G11C16/102

Abstract: A process of programming or reprogramming a reprogrammable onboard memory (5) comprises programming or reprogramming the onboard memory of several modules (M0, M1) in parallel through a multiple access bus (6) to which the modules are connected. In the case of blank flash memories, a process downloads code through the multiple access bus (6) and executes the code, eliminating all external constraints (such as frequency, binary throughput). The process is more particularly intended to apply to onboard flash type memories.

Abstract translation: 编程或重新编程可重编程板载存储器（5）的过程包括通过与模块连接的多址总线（6）并行地编程或重新编程几个模块（M 0，M 1）的板上存储器。 在空白闪速存储器的情况下，处理通过多路访问总线（6）下载代码并执行代码，消除所有外部约束（诸如频率，二进制吞吐量）。 该过程更特别地旨在应用于板载闪存型存储器。

公开(公告)号：US20060195723A1

公开(公告)日：2006-08-31

申请号：US11351344

申请日：2006-02-08

Applicant: Frederic Bancel ,  David Hely

Inventor： Frederic Bancel ,  David Hely

IPC: G06F11/00

CPC classification number: G11C7/24 ,  G01R31/31719 ,  G01R31/318536 ,  G11C29/1201 ,  G11C29/46

Abstract: An electronic circuit includes a logic circuit formed from a plurality of logic units. The electronic circuit also includes a plurality of memory units capable of forming a shift register, capable of being connected to the logic units, and having terminals for reception of command signals to write data into the logic units and to read data from the logic units. The electronic circuit further includes an access controller having a plurality of outputs connected to the terminals of the memory units and capable of applying the command signals to the outputs. In addition, the electronic circuit includes a scrutinizing module capable of measuring at least one signal between at least one of the outputs of the access controller and the reception terminal of at least one of the memory units, determining if the at least one measured signal differs from the at least one command signal applied to the at least one output by the access controller, and blocking formation of the shift register if a difference is determined.

Abstract translation: 电子电路包括由多个逻辑单元形成的逻辑电路。 电子电路还包括能够形成移位寄存器的多个存储器单元，能够连接到逻辑单元，并且具有用于接收命令信号的端子以将数据写入逻辑单元并从逻辑单元读取数据。 电子电路还包括具有连接到存储器单元的端子的多个输出并且能够将命令信号施加到输出的存取控制器。 此外，电子电路包括检查模块，该检查模块能够测量访问控制器的至少一个输出和至少一个存储器单元的接收端之间的至少一个信号，确定至少一个测量信号是否不同 从所述访问控制器施加到所述至少一个输出的所述至少一个命令信号，以及如果确定了差异则阻止所述移位寄存器的形成。

公开(公告)号：US07098838B2

公开(公告)日：2006-08-29

申请号：US11191614

申请日：2005-07-28

Applicant: Laurent Simony

Inventor： Laurent Simony

IPC: H03M1/12

CPC classification number: H03M1/18

Abstract: An amplified reading device includes an adjustable gain amplifier AMP receiving analog information and of which 2j successive gain values, respectively adjustable by 2j successive values of a first control word of j bits, follow a geometric progression of ratio a; an analog/digital converter CAN connected to the output of the amplifier, having an adjustable input full scale, of which 2k different values, respectively adjustable, for each gain value, from 2k successive values of a second control word of k bits, follow a geometric progression of ratio a1/2 k, the converter delivering a digital code corresponding to the analog information amplified by an overall gain, the value of which depends on the gain value of the amplifier and on that of the full scale, and a controller MCM designed to deliver the first and second control words.

公开(公告)号：US20060181724A1

公开(公告)日：2006-08-17

申请号：US11352893

申请日：2006-02-13

Applicant: Jacques Dumarest

Inventor： Jacques Dumarest

IPC: G06F3/12

CPC classification number: G09G5/04 ,  G09G5/006 ,  G09G2320/02 ,  G09G2320/0666 ,  G09G2340/0428

Abstract: This image processing method for the conversion of an image with a first number of bits per pixel, for example 16 bits per pixel, into an image with a second number of bits per pixel, for example 18 bits per pixel, includes generating additional coding bit values for the components (Ri, Gi, Bi) of each pixel starting from the component values of adjacent pixels and generating the converted signal from the additional coding bits.

Abstract translation: 用于将具有每像素的第一位数（例如每像素16位）的图像转换成具有每像素的第二数量位的图像（例如每像素18位）的图像处理方法包括产生附加编码位 从相邻像素的分量值开始的每个像素的分量（R i，i，G i，B i i i）的值，并且生成转换的 来自附加编码位的信号。