公开(公告)号：US10446682B2

公开(公告)日：2019-10-15

申请号：US16244076

申请日：2019-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US10446663B2

公开(公告)日：2019-10-15

申请号：US16121567

申请日：2018-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tan-Ya Yin ,  Chia-Wei Huang

IPC: H01L31/119 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/308 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first fin segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.

公开(公告)号：US10446559B2

公开(公告)日：2019-10-15

申请号：US16053748

申请日：2018-08-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Chao-An Liu ,  Ching-Hsiang Chang ,  Yi-Wei Chen

IPC: H01L27/108 ,  H01L21/308 ,  H01L21/02 ,  H01L21/306 ,  H01L21/033 ,  H01L21/027

Abstract: A method of fabricating a DRAM includes providing a substrate. Later, a first mask layer is formed to cover the substrate. The first mask layer includes a hydrogen-containing silicon nitride layer and a silicon oxide layer. The hydrogen-containing silicon nitride layer has the chemical formula: SixNyHz, wherein x is between 4 and 8, y is between 3.5 and 9.5, and z equals 1. After that, the first mask layer is patterned to form a first patterned mask layer. Next, the substrate is etched by taking the first patterned mask layer as a mask to form a word line trench. Subsequently, the first patterned mask layer is removed entirely. Finally, a word line is formed in the word line trench.

公开(公告)号：US10446554B2

公开(公告)日：2019-10-15

申请号：US16027267

申请日：2018-07-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Chieh-Te Chen

IPC: G11C11/404 ,  H01L27/108 ,  H01L49/02 ,  G11C11/4074 ,  G11C7/02

Abstract: A semiconductor memory device includes a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.

公开(公告)号：US10444622B2

公开(公告)日：2019-10-15

申请号：US15892935

申请日：2018-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yeh Wu ,  Chia-Wei Huang ,  Yung-Feng Cheng

IPC: G06F17/50 ,  G03F1/70 ,  G03F7/20 ,  G03F1/36

Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.

公开(公告)号：US20190304909A1

公开(公告)日：2019-10-03

申请号：US16446590

申请日：2019-06-19

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Shih-Fang Tzou ,  Fu-Che Lee ,  Chien-Cheng Tsai ,  Feng-Ming Huang

IPC: H01L23/528 ,  H01L29/06 ,  H01L21/762 ,  H01L27/108 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.

公开(公告)号：US20190304777A1

公开(公告)日：2019-10-03

申请号：US15964031

申请日：2018-04-26

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee ,  Ying-Chih Lin ,  Gang-Yi Lin

IPC: H01L21/02 ,  H01L21/033

Abstract: The present invention provides a method for fabricating a hard mask, comprising: firstly, a first material layer and a second material layer are provided on the first material layer, a cell region and a peripheral region are defined thereon, and then a plurality of sacrificial patterns and a plurality of spacers are formed in the cell region on the second material layer, each two spacers are located at two sides of each of the sacrificial patterns. Afterwards, a first etching step is performed to remove the sacrificial patterns, a second etching step is performed to remove a portion of the second material layer and expose a portion of the first material layer within the cell region, and a third etching step is performed to remove portions of the first material layer, so as to forma plurality of first recesses in the first material layer.

公开(公告)号：US10431497B1

公开(公告)日：2019-10-01

申请号：US15951192

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Kuan-Hao Tseng ,  Yu-Hsiang Lin ,  Shih-Hung Tsai ,  Yu-Ting Tseng

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/321 ,  H01L21/28

Abstract: A manufacturing method of an epitaxial fin-shaped structure includes the following steps. A substrate is provided. A recess is formed in the substrate. An epitaxial layer is formed on the substrate. The epitaxial layer is partly formed in the recess and partly formed outside the recess. The epitaxial layer has a dent formed on the top surface of the epitaxial layer, and the dent is formed corresponding to the recess in a thickness direction of the substrate. A nitride layer is conformally formed on the epitaxial layer. An oxide layer is formed on the nitride layer. A first planarization process is performed to remove a part of the oxide layer, and the first planarization process is stopped on the nitride layer. The epitaxial layer in the recess is patterned for forming at least one epitaxial fin-shaped structure.

公开(公告)号：US20190296020A1

公开(公告)日：2019-09-26

申请号：US16412447

申请日：2019-05-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/764 ,  H01L29/06 ,  H01L29/49

Abstract: A semiconductor structure includes a semiconductor substrate having a trench isolation region formed therein. A conductive gate electrode is buried in the trench isolation region. An air gap is disposed between the conductive gate electrode and the semiconductor substrate.

公开(公告)号：US20190296019A1

公开(公告)日：2019-09-26

申请号：US15961827

申请日：2018-04-24

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Han Wu ,  Li-Wei Feng ,  Shih-Han Hung ,  Fu-Che Lee ,  Chien-Cheng Tsai

IPC: H01L27/108 ,  H01L21/768

Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.