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621.发明授权公开(公告)号：US10531132B2
公开(公告)日：2020-01-07
申请号：US15856509
申请日：2017-12-28
Inventor： Udit Kumar , Bharat Jauhari , Chandandeep Singh Pabla
IPC: H04N21/438 , H04N21/234 , H04N21/44 , H04N5/44 , H04N21/433 , H04N21/434 , H04N21/482
Abstract: A channel stream is received and demultiplexed into a video packetized elementary stream (PES), audio packetized elementary stream (PES), and program clock reference (PCR). Indexing circuitry stores the video PES and the audio PES in a buffer, locates a presentation time stamp (PTS) in the video PES and stores that PTS in the buffer, locates a start of each group of pictures (GOP) in the video PES and stores those locations in the buffer, and locates a PTS in the audio PES and stores that PTS in the buffer. Control circuitry empties the buffer of an oldest GOP in the video PES if the PCR is greater than the PTS of a second oldest GOP stored in the buffer, and empties the buffer of each PES packet of the audio PES that has a PTS that is less than the PTS of the oldest GOP stored.
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公开(公告)号：US10520552B2
公开(公告)日：2019-12-31
申请号：US15455321
申请日：2017-03-10
Inventor： K. R. Hariharasudhan , Frank J. Sigmund
IPC: G01R31/36 , G01R31/367 , G01R31/3842
Abstract: An electronic device includes a processor coupled to a battery and to determine whether the battery is being charged or discharged. If the battery being is being discharged, the processor operates to calculate an amount by which the battery has discharged since a preceding calculation of remaining capacity of the battery, compensate the amount by which the battery has discharged for a condition of the battery, and calculate a remaining capacity of the battery as a function of the amount by which the battery has discharged. If the battery is being charged, the processor operates to calculate an amount by which the battery has charged since a preceding calculation of remaining capacity of the battery, compensate the amount by which the battery has charged for a condition of the battery, and calculate the remaining capacity of the battery as a function of the amount by which the battery has charged.
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公开(公告)号：US20190342960A1
公开(公告)日：2019-11-07
申请号：US16514275
申请日：2019-07-17
Applicant: STMicroelectronics International N.V.
Inventor： Akshat JAIN , Ranajay MALLIK
Abstract: A circuit includes a voltage converter converting a source voltage to a supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between the first node and a second node. Feedback circuitry compares the voltage at the second node to first and second overvoltages, and selectively couples the second node to the feedback node based thereupon. Impedance circuitry is coupled between the first node and a third node. A light emitting diode (LED) chain is coupled to the third node, and is selectively turned on and off as a function of the selective coupling of the second node to the feedback node by the feedback circuitry.
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624.发明申请公开(公告)号：US20190319454A1
公开(公告)日：2019-10-17
申请号：US15952466
申请日：2018-04-13
Inventor： Radhakrishnan SITHANANDAM , Divya AGARWAL , Jean JIMENEZ , Malathi KAR
Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated SCR device. The SCR device may include an embedded field effect transistor (FET) having an insulated gate that receives a trigger signal from an ESD detection circuit. The SCR device may alternatively include a variable substrate resistor having an insulated gate that receives a trigger signal from an ESD detection circuit.
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625.发明申请公开(公告)号：US20190288693A1
公开(公告)日：2019-09-19
申请号：US15924584
申请日：2018-03-19
Applicant: STMicroelectronics International N.V.
Inventor： Nitin Gupta , Jeet Narayan Tiwari
Abstract: Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.
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Patent Agency Ranking
公开(公告)号：US10405384B2
公开(公告)日：2019-09-03
申请号：US16106593
申请日：2018-08-21
Applicant: STMicroelectronics International N.V.
Inventor： Akshat Jain , Ranajay Mallik
Abstract: A circuit includes a voltage converter converting source voltage to supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between first and second node nodes. Feedback circuitry couples the second node to the feedback node when a voltage at the second node exceeds a first overvoltage, in a first mode of operation. The feedback circuitry couples the second node to the feedback node when the voltage at the second node exceeds a second overvoltage less than the first overvoltage, in a second mode of operation. Impedance circuitry is coupled between the first node and a third node and generates an auxiliary supply voltage and an auxiliary ground voltage when the circuit is in both the first and second modes, the auxiliary supply voltage being less than the supply voltage in both the first and second modes.
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627.发明授权公开(公告)号：US10382033B2
公开(公告)日：2019-08-13
申请号：US15653034
申请日：2017-07-18
Applicant: STMicroelectronics International N.V.
Inventor： Prashant Singh
Abstract: A power supply voltage detector circuit monitors a ramping supply voltage and selectively enables a voltage divider for operation to divide the ramping supply voltage in response to the ramping supply voltage exceeding a first threshold. Additionally, a variable resistance of the voltage divider is changed in response to the ramping supply voltage exceeding a second threshold. A voltage output from the voltage divider is used to generate a bandgap voltage used as a reference voltage in comparison operations for controlling enabling of the voltage divider and selection of the variable resistance.
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公开(公告)号：US20190190688A1
公开(公告)日：2019-06-20
申请号：US15846560
申请日：2017-12-19
Applicant: STMicroelectronics International N.V.
Inventor： Rupesh Singh , Ankur Bal
IPC: H04L7/00
Abstract: Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.
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629.发明申请公开(公告)号：US20190158070A1
公开(公告)日：2019-05-23
申请号：US15815989
申请日：2017-11-17
Applicant: STMicroelectronics International N.V.
Inventor： Mohit Singh , Ankur Bal
IPC: H03H17/06
Abstract: A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.
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公开(公告)号：US10291389B1
公开(公告)日：2019-05-14
申请号：US15923119
申请日：2018-03-16
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha
IPC: H03L7/087 , H04L7/033 , H04L7/00 , H03L7/099 , H04B1/7073
Abstract: A modulation circuit includes a locked loop circuit with two-point modulation control and a phase-frequency detector configured to compare a reference frequency signal with a feedback frequency signal. A two-point modulation control circuit includes a first modulation path having a controllable gain and coupled to one of the first and second modulation control points and a second modulation path coupled to another of the first and second modulation control points. Gain matching of the first and second modulation paths is accomplished through the operation of a calibration circuit. The calibration circuit includes a phase detector circuit configured to compare the reference frequency signal with the feedback frequency signal to generate a phase detect signal, and a gain control circuit configured to adjust the controllable gain of the first modulation path as a function a correlation of the phase detect signal with signs of the modulation data.
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