Low voltage, master-slave flip-flop
    631.
    发明授权

    公开(公告)号:US10277207B1

    公开(公告)日:2019-04-30

    申请号:US15892308

    申请日:2018-02-08

    Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

    LOW LEAKAGE LOW DROPOUT REGULATOR WITH HIGH BANDWIDTH AND POWER SUPPLY REJECTION, AND ASSOCIATED METHODS

    公开(公告)号:US20190113943A1

    公开(公告)日:2019-04-18

    申请号:US16217872

    申请日:2018-12-12

    Abstract: An electronic device including a low dropout regulator having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node of the electronic device. A method for operating the device to switch into a power on mode includes: turning on the low dropout regulator, removing a DC bias from the second conduction terminal of the transistor, and turning on the transistor. A method for operating the device to switch into a power down mode includes: turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the low dropout regulator.

    High speed data weighted averaging architecture

    公开(公告)号:US10218380B1

    公开(公告)日:2019-02-26

    申请号:US16036004

    申请日:2018-07-16

    Abstract: Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.

    Generic bit error rate analyzer for use with serial data links

    公开(公告)号:US10198331B2

    公开(公告)日:2019-02-05

    申请号:US15475277

    申请日:2017-03-31

    Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.

    Low leakage low dropout regulator with high bandwidth and power supply rejection

    公开(公告)号:US10198014B2

    公开(公告)日:2019-02-05

    申请号:US15475266

    申请日:2017-03-31

    Abstract: A low dropout regulator produces output at an intermediate node. A resistive divider is coupled between the intermediate node and ground and provides a feedback signal to the low dropout regulator. A transistor has a first conduction terminal coupled to the intermediate node and a second conduction terminal coupled to an output node. A first impedance is coupled to the output node, a first switch selectively couples the first impedance to a supply node, a second impedance coupled to the output node, and a second switch selectively couples the second impedance to a ground node. Control circuitry is coupled to the control terminal of the transistor and to control terminals of the first and second switches. The control circuitry switches the electronic device to a power down mode by turning off transistor, closing the first and second switches, and turning off the low dropout regulator.

    Battery DC impedance measurement
    639.
    发明授权

    公开(公告)号:US10191118B2

    公开(公告)日:2019-01-29

    申请号:US15809433

    申请日:2017-11-10

    Inventor: Daniel Ladret

    Abstract: The state of charge of a rechargeable battery is determined by calculating the DC impedance of the battery. The impedance is calculated by: performing a two different constant current discharges of the battery at a first and second C-rates, respectively; measuring the voltage and current during the interval of each constant current discharge and calculating the amount of charge extracted from the battery up to a point where the battery voltage drops to a threshold value; calculating the state of charge of the battery; and calculating the DC impedance of the battery as a function of the difference between the battery voltages and discharge currents for the two different discharges.

    Video encoders/decoders and video encoding/decoding methods for video surveillance applications

    公开(公告)号:US10187650B2

    公开(公告)日:2019-01-22

    申请号:US14306673

    申请日:2014-06-17

    Abstract: Video encoders and decoders and video encoding and decoding methods are provided. A video encoder includes an input buffer configured to receive a video data stream and to supply current frame data, a frame buffer configured to store reconstructed frame data, and an encoder circuit configured to read reference frame data from the frame buffer, to encode the current frame data received from the input buffer using the reference frame data and to write the reconstructed frame data to the frame buffer. The encoder circuit may be configured to write the reconstructed frame data by overwriting the reference frame data in the frame buffer.

Patent Agency Ranking