公开(公告)号：US06934192B2

公开(公告)日：2005-08-23

申请号：US10178796

申请日：2002-06-24

Applicant: François Tailliet ,  Francesco La Rosa

Inventor： François Tailliet ,  Francesco La Rosa

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/08

Abstract: An electrically programmable and erasable memory includes memory cells, with each memory cell including a floating gate transistor and an access transistor. The floating gate transistor has a first terminal connected to the access transistor. The memory includes circuitry for respectively applying during an erasing phase a first signal, and a second signal on the control gate and on a second terminal of the floating gate transistors of the memory cells to be erased. The circuitry also applies to the gates of the corresponding access transistors of the memory cells to be erased a signal having a voltage that is different from a voltage of the first signal and has a low or zero potential difference with respect to a voltage of the second signal. The memory is protected against the effects from a breakdown of the gate oxide of an access transistor.

Abstract translation: 电可编程和可擦除存储器包括存储单元，其中每个存储单元包括浮栅晶体管和存取晶体管。 浮栅晶体管具有连接到存取晶体管的第一端。 存储器包括用于在擦除阶段期间分别施加第一信号的电路和在要擦除的存储器单元的控制栅极和浮置栅极晶体管的第二端子上的第二信号。 该电路还适用于存储器单元的相应存取晶体管的栅极，以被擦除具有与第一信号的电压不同的电压的信号，并且相对于第二个电压的电压具有低或零电位差 信号。 保护存储器不受存取晶体管栅极氧化物击穿的影响。

公开(公告)号：US20050174172A1

公开(公告)日：2005-08-11

申请号：US11055925

申请日：2005-02-11

Applicant: Philippe Sirito-Olivier

Inventor： Philippe Sirito-Olivier

IPC: H03F1/30 ,  H03F1/36 ,  H03F3/45

CPC classification number: H03F3/45098 ,  H03F1/302 ,  H03F3/45538

Abstract: The method controls, in a feedback mode, a common collector or common drain amplifier, biased with a voltage applied on a bias node produced by a biasing circuit that generates a temperature compensated reference voltage from which the bias voltage applied on the bias node of the amplifier is derived. The quiescent voltage on the output node of the amplifier is made substantially independent from temperature by sensing the quiescent voltage on the output node, and adjusting the voltage applied on the bias node of the amplifier based upon the difference between the reference voltage and the sensed quiescent voltage for maintaining it constant.

Abstract translation: 该方法在反馈模式下控制公共集电极或公共漏极放大器，该偏置电压施加在由偏置电路产生的偏置电路上的电压，该偏置电路产生温度补偿的参考电压，从而施加在偏置节点上的偏置电压 派生放大器。 放大器的输出节点上的静态电压通过感测输出节点上的静态电压而基本上与温度无关，并且基于参考电压和感测到的静态之间的差异来调节施加在放大器的偏置节点上的电压 电压保持恒定。

公开(公告)号：US20050174157A1

公开(公告)日：2005-08-11

申请号：US11051137

申请日：2005-02-04

Applicant: Pietro Calo' ,  Philippe Sirito-Olivier

Inventor： Pietro Calo' ,  Philippe Sirito-Olivier

IPC: H03H7/25 ,  H03L5/00

CPC classification number: H03H7/25

Abstract: A variable attenuation network of an input voltage on an input node produces an attenuated voltage on an output node of the network, and includes a voltage divider with multiple-taps that are selectable for producing the attenuated voltage from a voltage applied on the terminals of the voltage divider. The attenuation network produces an output voltage with an attenuation ratio that is determined with at least twice the resolution of the voltage divider, because it includes at least one resistor that may be shorted by a low impedance by-pass line controlled by a switch and alternatively connected between the selected intermediate tap or any one of the two terminals of the voltage divider and the output node of the variable attenuation network, the input node of the attenuation network or a common ground node, respectively. By using more than one shortable resistor, multiple levels of resolution may be obtained.

Abstract translation: 输入节点上的输入电压的可变衰减网络在网络的输出节点上产生衰减电压，并且包括具有多个抽头的分压器，所述分压器可选择用于根据施加在所述输入节点的端子上的电压产生衰减电压 分压器 衰减网络产生具有衰减比的输出电压，该衰减比由分压器的分辨率的至少两倍决定，因为它包括至少一个电阻器，该电阻器可被由开关控制的低阻抗旁路线路短路， 连接在所选择的中间抽头或分压器的两个端子中的任一个和可变衰减网络的输出节点，衰减网络的输入节点或公共接地节点之间。 通过使用多于一个的短路电阻，可以获得多级分辨率。

公开(公告)号：US06913198B2

公开(公告)日：2005-07-05

申请号：US10873915

申请日：2004-06-22

Applicant: Ludovic Ruat ,  Olivier Ferrand ,  Bruno Gailhard

Inventor： Ludovic Ruat ,  Olivier Ferrand ,  Bruno Gailhard

IPC: G06K17/00 ,  G06K7/00 ,  G06K7/08 ,  G06K19/06

CPC classification number: G06K7/0069 ,  G06K7/0013 ,  G06K7/006 ,  G06K7/0086 ,  Y10T307/937

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

Abstract translation: 智能卡读取器包括用于接收智能卡的壳体，微处理器和用于将微处理器连接到接收的智能卡的连接器，用于在其间建立通信。 电压源基于智能卡被接收在外壳中而向微处理器提供电源电压。 智能卡读卡器还包括插入在电压源和微处理器的电源端之间的第一开关。 当接收到的智能卡处于壳体行程结束时，第一开关闭合，使得电源电压被提供给微处理器，并且当接收到的智能卡不再在外壳中行进结束时打开 使得不向微处理器提供电源电压。

公开(公告)号：US06906588B2

公开(公告)日：2005-06-14

申请号：US10451086

申请日：2001-12-14

Applicant: Michel Mouret ,  Marc Sabut ,  François Van Zanten

Inventor： Michel Mouret ,  Marc Sabut ,  François Van Zanten

IPC: H03G7/08 ,  H03F3/45

CPC classification number: H03G7/08

Abstract: A variable-gain amplifier with a differential input and differential output, including an attenuator block, receiving an input voltage and providing, on several outputs, voltages, each of which is equal to the attenuated input voltage; differential transconductor elements, each having a first input connected to a respective output of the attenuator block, and generating first and second positive currents and first and second negative currents; a current source assembly adapted to controlling the transconductance of each differential transconductor element according to an analog control signal; and an output block converting first and second input currents into a differential output voltage and providing a second input of each differential transconductor element with a feedback voltage depending on the output voltage.

Abstract translation: 具有差分输入和差分输出的可变增益放大器，包括衰减器块，接收输入电压并在几个输出上提供电压，每个电压等于衰减的输入电压; 差分跨导元件，每个具有连接到衰减器块的相应输出的第一输入，以及产生第一和第二正电流以及第一和第二负电流; 电流源组件，其适于根据模拟控制信号控制每个差分跨导元件的跨导; 以及输出块，其将第一和第二输入电流转换成差分输出电压，并且根据输出电压提供具有反馈电压的每个差分跨导元件的第二输入。

公开(公告)号：US20050114732A1

公开(公告)日：2005-05-26

申请号：US10670996

申请日：2003-09-24

Applicant: Pascal Janin ,  Michael Giovannini ,  Corinne Ianigro

Inventor： Pascal Janin ,  Michael Giovannini ,  Corinne Ianigro

IPC: G06F1/24 ,  G06F11/00

CPC classification number: G06F11/0757

Abstract: A method for operating a watchdog timer associated with a microcontroller that generates refresh commands for the watchdog timer is provided. The refresh commands are separated by a time interval receiving the refresh commands by the watchdog timer, and generating a microcontroller reset command by the watchdog timer when a time interval separating successively received refresh commands is not within the predetermined range. In particular, the generating includes staring a refresh countdown on each receipt of a refresh command by the watchdog timer. A reset countdown is started if the refresh countdown has timed out, and if the refresh countdown has not timed out when a next refresh command is received, then the next refresh command does not restart the reset countdown. The microcontroller reset command is generated if the reset countdown has timed out.

Abstract translation: 提供了一种用于操作与产生用于看门狗定时器的刷新命令的微控制器相关联的看门狗定时器的方法。 刷新命令由看门狗定时器接收刷新命令的时间间隔分开，并且当连续接收到的刷新命令的时间间隔不在预定范围内时，由看门狗定时器产生微控制器复位命令。 特别地，生成包括在看门狗定时器的每次接收到刷新命令时开始刷新倒计时。 如果刷新倒计时已经超时，则启动复位倒计时，如果接收到下一个刷新命令时刷新倒数计时没有超时，则下一个刷新命令不会重新启动复位倒计时。 如果复位倒计时已超时，则会产生微控制器复位命令。

公开(公告)号：US06897689B2

公开(公告)日：2005-05-24

申请号：US10641337

申请日：2003-08-14

Applicant: Francesco La Rosa

Inventor： Francesco La Rosa

IPC: H03K17/22 ,  H03L7/00

CPC classification number: H03K17/223

Abstract: A power on reset circuit (POR) includes a first reset circuit for delivering a first reset signal when a supply voltage of the POR circuit is between a first low threshold and a first high threshold, and a second reset circuit for delivering a second reset signal when the supply voltage is between a second low threshold and a second high threshold. The second high threshold is less than the first high threshold. The POR circuit further includes at least one electrically erasable and programmable non-volatile memory cell. A delivery circuit outputs the first reset signal or the second reset based upon whether the at least one electrically erasable and programmable non-volatile memory cell is in an erased or programmed state. The POR circuit has a threshold for outputting the first or second reset signal that is programmable according to the intended application.

Abstract translation: 上电复位电路（POR）包括第一复位电路，用于当POR电路的电源电压处于第一低阈值和第一高阈值之间时传送第一复位信号;以及第二复位电路，用于传送第二复位信号 当电源电压处于第二低阈值和第二高阈值之间时。 第二个高阈值小于第一个高阈值。 POR电路还包括至少一个电可擦除和可编程的非易失性存储单元。 输送电路基于所述至少一个电可擦除可编程非易失性存储单元是否处于擦除或编程状态来输出第一复位信号或第二复位。 POR电路具有用于输出根据预期应用可编程的第一或第二复位信号的阈值。

公开(公告)号：US20050104659A1

公开(公告)日：2005-05-19

申请号：US10944531

申请日：2004-09-17

Applicant: Philippe Sirito-Olivier ,  Pietro Calo

Inventor： Philippe Sirito-Olivier ,  Pietro Calo

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F2203/45352 ,  H03F2203/45361 ,  H03F2203/45392

Abstract: A Darlington differential amplifier includes a differential pair of Darlington transistors, with each pair including a first transistor and a second transistor connected in cascade to the first transistor. The first transistor is controlled by an externally generated voltage and drives the second transistor. The first and second transistors each include first and second conducting terminals, with the first conducting terminals being connected together and forming an output node of the amplifier. A first degeneration impedance is connected between the second conduction terminals of the second transistors in the pair of Darlington transistors. A second degeneration impedance is connected between the second conduction terminals of the first transistors in the pair of Darlington transistors for reducing harmonic distortion of the amplifier.

Abstract translation: 达林顿差分放大器包括达林顿晶体管的差分对，每对包括与第一晶体管级联连接的第一晶体管和第二晶体管。 第一晶体管由外部产生的电压控制并驱动第二晶体管。 第一和第二晶体管各自包括第一和第二导电端子，其中第一导电端子连接在一起并形成放大器的输出节点。 第一退化阻抗连接在该对达林顿晶体管中的第二晶体管的第二导通端之间。 第二退化阻抗连接在该对达林顿晶体管中的第一晶体管的第二导通端之间，用于减小放大器的谐波失真。

公开(公告)号：US20050078054A1

公开(公告)日：2005-04-14

申请号：US10926786

申请日：2004-08-26

Applicant: Eric Cirot ,  Michel Barou ,  Danika Chaussy

Inventor： Eric Cirot ,  Michel Barou ,  Danika Chaussy

IPC: H04N5/14 ,  H04N5/21

CPC classification number: H04N5/142

Abstract: A device for producing a video image sharpness improvement signal (DOC21-DOC22), with black level clipping of an associated video signal, comprises a differential transconductance stage processing the video signal and whose bias currents (Imax) are directly proportional to the active component (ΔV) of the video signal so as to bring about a black level sharpness improvement signal clipping.

Abstract translation: 用于产生视频图像锐度改善信号（DOC21-DOC22）的装置，具有相关视频信号的黑电平限幅，包括处理视频信号的差分跨导级并且其偏置电流（Imax）与有效分量成正比（ DeltaV），以产生黑色电平锐度改善信号限幅。

公开(公告)号：US20050077924A1

公开(公告)日：2005-04-14

申请号：US10929359

申请日：2004-08-27

Applicant: Cyrille Dray

Inventor： Cyrille Dray

IPC: G11C16/12 ,  H03F3/45

CPC classification number: G11C16/12

Abstract: A switch arrangement for switching a node between three supply voltages based on two control signals. The switch arrangement includes three circuits for connecting an output node with one of three nodes, each of which is set to a different voltage. The switch arrangement is controlled by six control signals that establish mutually exclusive switching modes and avoid combinational currents. The switch arrangement is also designed to allow the use of MOS transistors having a low nominal voltage, with a value that is lower than the highest voltage to be switched. The switch arrangement is particularly adapted to supply power to non-volatile memory cells.

Abstract translation: 一种用于基于两个控制信号在三个电源电压之间切换节点的开关装置。 开关装置包括用于将输出节点与三个节点之一连接的三个电路，每个节点被设置为不同的电压。 开关布置由六个控制信号控制，这些控制信号建立互斥开关模式并避免组合电流。 开关装置还被设计为允许使用具有低额定电压的MOS晶体管，其值低于要切换的最高电压。 开关装置特别适于向非易失性存储单元供电。