公开(公告)号：US11663365B2

公开(公告)日：2023-05-30

申请号：US16928901

申请日：2020-07-14

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (ALPS) SAS

Inventor： Marc Benveniste ,  Fabien Journet ,  Fabrice Marinet

IPC: G06F21/44 ,  G06F21/72 ,  G06F21/75 ,  G06F1/08 ,  G06F3/12 ,  H04L9/32

CPC classification number: G06F21/75 ,  G06F1/08 ,  G06F3/1238 ,  G06F21/44 ,  G06F21/72 ,  H04L9/3236 ,  H04L9/3247

Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.

公开(公告)号：US20230152832A1

公开(公告)日：2023-05-18

申请号：US18052860

申请日：2022-11-04

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jimmy FORT

IPC: G05F1/59 ,  G05F1/575 ,  G05F1/46

CPC classification number: G05F1/59 ,  G05F1/575 ,  G05F1/468

Abstract: Provided is a voltage regulator supplying a first voltage on a first output node and comprising a first input transistor of a non-inverting stage and a second biasing transistor of the non-inverting stage. The first and second transistors are coupled in series, in this order, between the first node and a second node of application of a second reference voltage. The second transistor is being configured to be controlled by a third voltage depending on the first voltage.

公开(公告)号：US11652512B2

公开(公告)日：2023-05-16

申请号：US17294978

申请日：2019-11-28

Applicant: STMicroelectronics (Rousset) SAS ,  Proton World International N.V.

Inventor： Olivier Van Nieuwenhuyze ,  Alexandre Charles

IPC: H04W4/80 ,  H04B5/00 ,  G06F9/445

CPC classification number: H04B5/0056 ,  G06F9/44505

Abstract: In an embodiment, an NFC controller of an NFC device is configured to transmit, after the detection, by the NFC controller, of an NFC reader in relation with a first NFC transaction and prior to receiving an application selection command from the NFC reader, an application selection message to a transaction handling element of the NFC device.

公开(公告)号：US11640921B2

公开(公告)日：2023-05-02

申请号：US17068112

申请日：2020-10-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Abderrezak Marzaki

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/16 ,  H01L25/18

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

公开(公告)号：US11637144B2

公开(公告)日：2023-04-25

申请号：US17409612

申请日：2021-08-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin

IPC: H01L45/00 ,  H01L27/24

Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.

公开(公告)号：US11626862B2

公开(公告)日：2023-04-11

申请号：US17251738

申请日：2019-06-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Tramoni ,  Jimmy Fort

IPC: G06F1/3287 ,  H03K3/0233 ,  H03K17/687

Abstract: An embodiment of the present disclosure relates to a circuit of cyclic activation of an electronic function comprising a hysteresis comparator controlling the charge of a capacitive element powering the function.

公开(公告)号：US11626365B2

公开(公告)日：2023-04-11

申请号：US17226324

申请日：2021-04-09

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11524

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US20230085493A1

公开(公告)日：2023-03-16

申请号：US17942354

申请日：2022-09-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics Design and Application S.R.O.

Inventor： Jerome LACAN ,  Remi COLLETTE ,  Christophe EVA ,  Milan KOMAREK

IPC: G06F1/3225 ,  G06F1/3287 ,  H03K19/017

Abstract: A system includes a control unit configured to be electrically connected to an input of a memory via a communication interface. The control unit includes a first power supply sector configured to be powered when the control unit is in an operating mode and a second power supply sector configured to be powered when the control unit is in the operating mode and in a low consumption mode. In the first power supply sector, the control unit includes a first configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the operating mode. In the second power supply sector, the control unit includes a second configuration circuit operating to configure a polarization value of the input of the memory via the communication interface for the low consumption mode.

公开(公告)号：US20230085284A1

公开(公告)日：2023-03-16

申请号：US17993067

申请日：2022-11-23

Applicant: STMicroelectronics ( Rousset) SAS

Inventor： Abderrezak Marzaki ,  Yoann Goasduff ,  Virginie Bidal ,  Pascal Fornara

IPC: G01V7/04 ,  B81B3/00 ,  B81C1/00 ,  H01L49/02 ,  H01H37/04 ,  H01H37/32 ,  H01L21/3213 ,  H01L29/423

Abstract: A method for detecting orientation of an integrated circuit is disclosed. The method includes moving, in response to a gravitational force, a mobile metallic piece in an evolution zone of a housing. The housing is formed in an interconnect region of the integrated circuit. The housing includes walls defining the evolution zone. The walls are formed within multiple metallization levels of the interconnect region. The walls include a floor wall and a ceiling wall. At least one of the floor wall and ceiling wall incorporate a pointed element directing its pointed region towards the mobile metallic piece. The pointed element delimits an open crater in a concave part of a projection. The method further includes creating an electrical signal by movement of the mobile metallic piece at a plurality of electrically conducting elements positioned at boundary points of the evolution zone and detecting the electrical signal by a detector.

公开(公告)号：US11593664B2

公开(公告)日：2023-02-28

申请号：US16917414

申请日：2020-06-30

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Laurent Folliot ,  Pierre Demaj ,  Emanuele Plebani

IPC: G06N3/10 ,  G06N3/04 ,  G06N3/08

Abstract: A method can be performed prior to implementation of a neural network by a processing unit. The neural network comprising a succession of layers and at least one operator applied between at least one pair of successive layers. A computational tool generates an executable code intended to be executed by the processing unit in order to implement the neural network. The computational tool generates at least one transfer function between the at least one pair of layers taking the form of a set of pre-computed values.