公开(公告)号：US11721646B2

公开(公告)日：2023-08-08

申请号：US17159698

申请日：2021-01-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Pascal Fornara

IPC: H01L27/10 ,  H01L23/00 ,  G04F1/00 ,  H01L21/70 ,  H01L27/01

CPC classification number: H01L23/573 ,  G04F1/005 ,  H01L21/705 ,  H01L27/013 ,  H01L27/101

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunnelling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US11715705B2

公开(公告)日：2023-08-01

申请号：US16932082

申请日：2020-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Fabrice Marinet

IPC: H01L29/788 ,  G06F21/75 ,  G06F21/79 ,  H01L23/522 ,  H10B41/35 ,  H01L23/00 ,  G06F21/87

CPC classification number: H01L23/573 ,  G06F21/75 ,  G06F21/79 ,  H01L23/5223 ,  H01L23/576 ,  H01L29/7883 ,  H10B41/35 ,  G06F21/87

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

公开(公告)号：US11581401B2

公开(公告)日：2023-02-14

申请号：US17370397

申请日：2021-07-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: H01L29/00 ,  H01L29/04 ,  H01L29/66 ,  H01L29/861 ,  H01L29/868

Abstract: A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

公开(公告)号：US10971578B2

公开(公告)日：2021-04-06

申请号：US16596673

申请日：2019-10-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Abderrezak Marzaki ,  Pascal Fornara

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/283 ,  H01L21/306 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/06 ,  H01L27/10

Abstract: The disclosure concerns a capacitive component including a trench and, vertically in line with the trench, first portions of a first silicon oxide layer and first portions of second and third conductive layers including polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second and third layers.

公开(公告)号：US10388695B2

公开(公告)日：2019-08-20

申请号：US13659622

申请日：2012-10-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L27/16 ,  H01L35/02 ,  H01L23/38 ,  H01L35/34

Abstract: Method of wireless communication between a first device and a second device, in which, the first device and the second device comprising respectively a first thermoelectric generator and a second thermoelectric generator, the two thermoelectric generators being in thermal coupling, a first signal is generated within the first device, the first thermoelectric generator is electrically powered as a function of the first signal so as to create a first thermal gradient in the said first generator and a second thermal gradient in the second generator, and a second signal is generated within the second device on the basis of the electrical energy produced by the second thermoelectric generator in response to the said second thermal gradient.

公开(公告)号：US10317846B2

公开(公告)日：2019-06-11

申请号：US15868484

申请日：2018-01-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: G11C16/04 ,  H01L27/115 ,  G04F10/10 ,  G11C16/28 ,  G11C16/34 ,  G11C27/00 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  H01L29/51

Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

公开(公告)号：US20190122845A1

公开(公告)日：2019-04-25

申请号：US16222017

申请日：2018-12-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio Di-Giacomo ,  Brice Arrazat

IPC: H01H61/02 ,  B81B3/00 ,  H01H1/58 ,  H01H9/02

CPC classification number: H01H61/02 ,  B81B3/0021 ,  B81B2201/031 ,  B81B2203/053 ,  H01H1/58 ,  H01H9/02

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

公开(公告)号：US20180145040A1

公开(公告)日：2018-05-24

申请号：US15596767

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L23/573 ,  H01L21/31111 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/823475 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/585 ,  H01L24/03 ,  H01L24/06 ,  H01L27/088

Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

公开(公告)号：US09899476B2

公开(公告)日：2018-02-20

申请号：US14953692

申请日：2015-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L21/762 ,  H01L21/763 ,  H01L29/06 ,  H01L29/78 ,  H01L27/112

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20170309532A1

公开(公告)日：2017-10-26

申请号：US15648135

申请日：2017-07-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L23/04 ,  B81B3/00 ,  H01L49/02 ,  H01L23/522 ,  H01G5/18 ,  H01L27/06

CPC classification number: H01L23/04 ,  B81B3/0021 ,  B81B2201/0221 ,  H01G5/18 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.