公开(公告)号：US20140351509A1

公开(公告)日：2014-11-27

申请号：US14273528

申请日：2014-05-08

Applicant: ASMedia Technology Inc.

Inventor： Ming-Hui CHIU ,  Chia-Hsin CHEN ,  Yung-Chi HWANG

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0689 ,  G06F11/00 ,  G06F2003/0692 ,  G06F2212/262

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system is a redundancy array of independent disk 0 (RAID 0) system The disk array system includes a plurality of disks. The data processing method includes: receiving a reading command; determining whether to divide the reading command to a plurality of reading command segments according to the reading command; and assigning the reading command to a corresponding disk of the disks to read data stored in the corresponding disk accordingly when it is determined that the reading command is not divided.

Abstract translation: 提供了磁盘阵列系统和数据处理方法。 数据处理方法应用于磁盘阵列系统。 磁盘阵列系统是独立磁盘0（RAID 0）系统的冗余阵列。磁盘阵列系统包括多个磁盘。 数据处理方法包括：接收读取命令; 根据读取命令确定是否将读取命令划分为多个读取命令段; 以及当确定所述读取命令未被划分时，将所述读取命令分配给所述盘的相应盘以相应地读取存储在所述对应盘中的数据。

公开(公告)号：US20140325198A1

公开(公告)日：2014-10-30

申请号：US14252252

申请日：2014-04-14

Applicant: Asmedia Technology Inc.

Inventor： Chin-Lung WU ,  Sheng-Chang PENG

IPC: G06F9/445

CPC classification number: G06F9/445

Abstract: An electronic device comprises a first memory unit, a processing unit and an operating interface. The processing unit is electronically connected to the first memory unit. The operating interface is electronically connected to the processing unit. When the processing unit is communicated with a host device via the operating interface, the processing unit executes a loading program and transmits a notification signal to the host device. The host device transmits at least one control program to the first memory unit according to the notification signal. When the control program is transmitted, the processing unit is reset and then executes the control program stored in the first memory unit. The stored firmware can be added or modified, and the circuit layout is simplified.

Abstract translation: 电子设备包括第一存储器单元，处理单元和操作界面。 处理单元电连接到第一存储器单元。 操作界面电连接到处理单元。 当处理单元经由操作界面与主机设备通信时，处理单元执行加载程序并向主机设备发送通知信号。 主机设备根据通知信号将至少一个控制程序发送到第一存储器单元。 当发送控制程序时，处理单元被复位，然后执行存储在第一存储单元中的控制程序。 可以添加或修改存储的固件，并简化电路布局。

公开(公告)号：US20130268746A1

公开(公告)日：2013-10-10

申请号：US13858112

申请日：2013-04-08

Applicant: Ming-Wei Hsu

Inventor： Ming-Wei Hsu

IPC: G06F21/57

CPC classification number: G06F21/572 ,  G06F9/4401 ,  G06F11/1417

Abstract: A system-on-chip (SoC) and a booting method thereof are disclosed. The SoC is coupled to an external memory and includes a read only memory (ROM) and a processor. The ROM stores a first firmware image. The processor is coupled to the ROM. The processor reads the first firmware image from the ROM and verifies the state of the first firmware image. If the first firmware image is damaged, the processor reads a second firmware image from the external memory and verifies whether the second firmware image is legal. If the verification of the second firmware image succeeds, the processor reads and executes the second firmware image to perform a booting process.

Abstract translation: 公开了一种片上系统（SoC）及其引导方法。 SoC耦合到外部存储器，并且包括只读存储器（ROM）和处理器。 ROM存储第一固件映像。 处理器耦合到ROM。 处理器从ROM读取第一固件映像，并验证第一固件映像的状态。 如果第一固件映像损坏，则处理器从外部存储器读取第二固件映像，并验证第二固件映像是否合法。 如果第二固件映像的验证成功，则处理器读取并执行第二固件映像以执行引导处理。

公开(公告)号：US08291242B2

公开(公告)日：2012-10-16

申请号：US12624878

申请日：2009-11-24

Applicant: Ming-Hui Chiu

Inventor： Ming-Hui Chiu

IPC: G06F1/00 ,  G05F1/00 ,  G05F3/16 ,  H02M1/12

CPC classification number: G06F1/26

Abstract: The disclosure is related to a method for transforming voltage identification codes of a microprocessor. The method comprises the steps of: receiving a first voltage identification code of a first voltage regulation standard, wherein the first voltage identification code is in correspondence with a first voltage; and transforming the first voltage identification code into a second voltage identification code of a second voltage regulation standard, wherein the second voltage identification code is in correspondence with a second voltage, and the second voltage is the same as the first voltage.

Abstract translation: 本公开涉及一种用于转换微处理器的电压识别码的方法。 该方法包括以下步骤：接收第一电压调节标准的第一电压识别码，其中第一电压识别码与第一电压相对应; 以及将所述第一电压识别码变换为第二电压调节标准的第二电压识别码，其中所述第二电压识别码与第二电压相对应，并且所述第二电压与所述第一电压相同。

公开(公告)号：US20120191885A1

公开(公告)日：2012-07-26

申请号：US13353391

申请日：2012-01-19

Applicant: Li-Feng Kuo ,  Pao-Shun Tseng ,  Chin-Yu Chang

Inventor： Li-Feng Kuo ,  Pao-Shun Tseng ,  Chin-Yu Chang

IPC: G06F13/36

CPC classification number: G06F1/266

Abstract: A method for configuring charging ports and a controller applying the same are disclosed. The method includes recording a maximum permission value and a permitted value, and comparing the maximum permission value and the permitted value to determine whether the interface port can be used as a charging port when a device is connected to an interface port.

Abstract translation: 公开了一种用于配置充电端口的方法和应用该充电端口的控制器。 该方法包括记录最大许可值和允许值，并且比较最大允许值和允许值以确定当设备连接到接口端口时，接口端口是否可以用作充电端口。

公开(公告)号：US07948422B2

公开(公告)日：2011-05-24

申请号：US12632680

申请日：2009-12-07

Applicant: Ming-Hui Chiu

Inventor： Ming-Hui Chiu

IPC: H03M1/12

CPC classification number: H03M7/04

Abstract: The invention relates to a method for converting a voltage identification code includes the steps as follows. A special binary code range is obtained, and N special voltage identification codes corresponding to a special command are converted to N special binary codes under a converting relation, and the N special binary codes are used as the special binary code range. A first voltage identification code is converted to a corresponding first binary code under the converting relation. In addition, the first binary code and a first preset value are used to compute to obtain a second binary code, and the second binary code is not in the special binary code range.

Abstract translation: 本发明涉及一种转换电压识别码的方法，包括以下步骤。 获得特殊的二进制代码范围，并将与特殊命令相对应的N个特殊电压识别代码转换为转换关系下的N个特殊二进制代码，并将N个特殊二进制代码用作特殊的二进制代码范围。 第一电压识别码在转换关系下转换为对应的第一二进制码。 此外，第一二进制码和第一预设值用于计算以获得第二二进制码，并且第二二进制码不在特殊的二进制码范围内。

公开(公告)号：US20100169555A1

公开(公告)日：2010-07-01

申请号：US12632668

申请日：2009-12-07

Applicant: Chien-Ping Chung ,  Chia-Hsin Chen ,  Ming-Che Liu

Inventor： Chien-Ping Chung ,  Chia-Hsin Chen ,  Ming-Che Liu

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7206

Abstract: A method of writing data into flash memory based on OS file system is provided. The method includes steps of: obtaining a data start position of a data area in a first partition of a flash memory; converting the data start position into a first block number and a first page number; calculating an offset and adding the offset to the first page number to be an updated first page number when the first page number is not an integer; and, setting the first block number and the updated first page number as a new data start position of the data area and writing a first data according to the new data start position.

Abstract translation: 提供了一种基于OS文件系统将数据写入闪存的方法。 该方法包括以下步骤：获取快闪存储器的第一分区中的数据区的数据开始位置; 将数据开始位置转换成第一块号和第一页号; 当第一页数不是整数时，计算偏移量并将偏移量添加到第一页数作为更新的第一页数; 并且将第一块号和更新的第一页号设置为数据区的新数据开始位置，并根据新数据开始位置写入第一数据。

公开(公告)号：US20100153755A1

公开(公告)日：2010-06-17

申请号：US12631789

申请日：2009-12-04

Applicant: Ming-Hui Chiu

Inventor： Ming-Hui Chiu

IPC: G06F1/00

CPC classification number: G06F1/28 ,  G06F1/3215 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/152 ,  Y02D10/172

Abstract: A VID processor includes a plurality of buffers, comparators, multiplexers and a core processing unit. The buffer may store a plurality of parameter values and a plurality of offset values. The buffers storing the parameter values may be coupled to the corresponding comparators, and other buffers may be coupled to the corresponding multiplexers. The comparator may compare the VID with the parameter values in the coupled buffer and output a selecting signal to the corresponding multiplexer according to the comparison outcome. Thus, the multiplexer may select and output one of the offset values to the core processing unit from the coupled buffer to allow the core processing unit to adjust the VID according to the output of the multiplexer.

Abstract translation: VID处理器包括多个缓冲器，比较器，多路复用器和核心处理单元。 缓冲器可以存储多个参数值和多个偏移值。 存储参数值的缓冲器可以耦合到对应的比较器，并且其它缓冲器可以耦合到相应的多路复用器。 比较器可以将VID与耦合缓冲器中的参数值进行比较，并根据比较结果将选择信号输出到相应的多路复用器。 因此，多路复用器可以从耦合的缓冲器中选择并输出一个偏移值到核心处理单元，以允许核心处理单元根据多路复用器的输出来调整VID。

公开(公告)号：US20100153754A1

公开(公告)日：2010-06-17

申请号：US12624878

申请日：2009-11-24

Applicant: Ming-Hui CHIU

Inventor： Ming-Hui CHIU

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: The disclosure is related to a method for transforming voltage identification codes of a microprocessor. The method comprises the steps of: receiving a first voltage identification code of a first voltage regulation standard, wherein the first voltage identification code is in correspondence with a first voltage; and transforming the first voltage identification code into a second voltage identification code of a second voltage regulation standard, wherein the second voltage identification code is in correspondence with a second voltage, and the second voltage is the same as the first voltage.

Abstract translation: 本公开涉及一种用于转换微处理器的电压识别码的方法。 该方法包括以下步骤：接收第一电压调节标准的第一电压识别码，其中第一电压识别码与第一电压相对应; 以及将所述第一电压识别码变换为第二电压调节标准的第二电压识别码，其中所述第二电压识别码与第二电压相对应，并且所述第二电压与所述第一电压相同。

公开(公告)号：US20100077248A1

公开(公告)日：2010-03-25

申请号：US12564907

申请日：2009-09-22

Applicant: Ching-Yen Wu ,  Chi Chang

Inventor： Ching-Yen Wu ,  Chi Chang

IPC: G06F1/04

CPC classification number: G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.

Abstract translation: 提供了一种时钟发生装置及其方法以及使用其的计算机系统。 时钟发生装置包括PLL模块和调谐模块。 PLL模块接收参考时钟信号，并根据参考时钟信号和反馈信号之间的相位差产生输出时钟信号作为计算机系统的基本时钟。 PLL模块包括根据控制信号调整固有分频比的分频器，并对输出时钟信号进行分频处理以产生反馈信号。 与PLL模块耦合的调谐模块根据CPU的VID和反馈信号和参考时钟之一产生控制信号。 因此，可以同步调整作为计算机系统中的基本频率的输出时钟信号的组件的操作频率。