公开(公告)号：US20080104336A1

公开(公告)日：2008-05-01

申请号：US11553813

申请日：2006-10-27

申请人： Blaine D. Gaither ,  Judson E. Veazey ,  Patrick Knebel

发明人： Blaine D. Gaither ,  Judson E. Veazey ,  Patrick Knebel

IPC分类号： G06F12/00

CPC分类号： G06F12/0817

摘要： A method comprises, while a first device has ownership of a data unit, a second device issuing a request to perform a memory write of said data unit. The method further comprises a memory controller performing the memory write without changing ownership to the second device.

摘要翻译： 一种方法包括当第一设备具有数据单元的所有权时，第二设备发出执行所述数据单元的存储器写入的请求。 该方法还包括执行存储器写入而不改变对第二设备的所有权的存储器控​​制器。

公开(公告)号：US20080086601A1

公开(公告)日：2008-04-10

申请号：US11544690

申请日：2006-10-06

申请人： Blaine D. Gaither ,  Verna Knapp

发明人： Blaine D. Gaither ,  Verna Knapp

IPC分类号： G06F13/28

CPC分类号： G06F12/0824

摘要： A method for maintaining cache coherence comprises coordinating operations among a plurality of processors distributed among a plurality of nodes coupled by an interconnect fabric and managing cache coherence in a plurality of memory directories respectively associated with the processor plurality in combination with a node controller directory cache associated with a node controller coupled between the processor plurality and the interconnect fabric. The method further comprises maintaining memory coherence directory information comprising identifying processors within a node in a first portion of bits of a memory directory entry coupled to an associated processor in the node and identifying subsets of processors external to the node in the system in a second portion of bits.

摘要翻译： 一种用于维持高速缓存一致性的方法包括协调分配在由互连结构耦合的多个节点之间的多个处理器之间的操作，并且在多个存储器目录中分配与处理器多个存储器目录相关联的高速缓存一致性，与节点控制器目录缓存相关联 其中节点控制器耦合在处理器多个和互连结构之间。 该方法还包括维护存储器一致性目录信息，包括识别耦合到节点中的相关处理器的存储器目录条目的位的第一部分中的节点内的处理器，以及在第二部分中识别系统中节点外部的处理器的子集 的位。

公开(公告)号：US07051195B2

公开(公告)日：2006-05-23

申请号：US10002971

申请日：2001-10-26

申请人： Blaine D. Gaither ,  Robert J Brooks

发明人： Blaine D. Gaither ,  Robert J Brooks

IPC分类号： G06F13/18

CPC分类号： G06F9/383 ,  G06F9/30145 ,  G06F9/3842

摘要： In processing an instruction request, the invention determines whether the request is speculative or not based upon a bit field within the instruction. If the request is speculative, bus congestion and/or target memory is assessed for conditions and a decision is made, based on the conditions, as to whether or not to process the request. To facilitate the invention, certain bit fields within the instruction are encoded to identify the request as speculative or not. Additional bit fields may define a priority of a speculative request to influence the decision to process as based on the conditions. CPU architectures incorporating prefetch logic may be modified to recognize instructions encoded with speculation and priority identification fields to implement the invention in existing systems. Other logic, e.g., bus controllers and switches, may similarly process speculative requests to enhance system performance.

公开(公告)号：US06950135B2

公开(公告)日：2005-09-27

申请号：US09768477

申请日：2001-01-24

申请人： Bret A. McKee ,  Blaine D. Gaither ,  Michael J Mahon

发明人： Bret A. McKee ,  Blaine D. Gaither ,  Michael J Mahon

IPC分类号： G01S17/10 ,  G01S17/89 ,  G03B13/18 ,  G06K9/00 ,  H01L27/00 ,  H04N3/14 ,  H04N5/225 ,  H04N5/353 ,  H04N13/00 ,  H04N5/335

CPC分类号： G01S17/89 ,  G01S17/107

摘要： A digital image capture device including circuits capable of measuring the distance between the image capture device and an imaged object allows the capture of three-dimensional data of the surface of the object facing the image capture device. The distance data is obtained by the addition of a flash unit, and very high resolution timers to multiple pixels within the image capture device to measure the time required for the flash to reflect from the object. Since the speed of light is constant, the distance from the flash to the object to the image capture device may be calculated from the delay for the light from the flash to reach the device. Multiple pixels may be used to construct a three-dimensional model of the surface of the object facing the image capture device. Multiple images including distance data may be taken in order to generate a complete three-dimensional model of the surface of the object.

摘要翻译： 包括能够测量图像拍摄装置和成像对象之间的距离的电路的数字图像捕获装置允许捕获面向图像捕获装置的对象的表面的三维数据。 距离数据通过添加闪光单元获得，并且对于图像捕获设备内的多个像素进行非常高分辨率的定时器来测量闪光从物体反射所需的时间。 由于光速恒定，所以可以从闪光灯到达设备的延迟来计算从闪光到物体到摄像装置的距离。 可以使用多个像素来构建面向图像捕获装置的物体的表面的三维模型。 可以采用包括距离数据的多个图像，以便生成对象表面的完整的三维模型。

公开(公告)号：US06792550B2

公开(公告)日：2004-09-14

申请号：US09775404

申请日：2001-01-31

申请人： Benjamin D. Osecky ,  Blaine D. Gaither

发明人： Benjamin D. Osecky ,  Blaine D. Gaither

IPC分类号： G06F100

CPC分类号： G06F11/004 ,  G06F1/206 ,  G06F11/006 ,  G06F11/20 ,  G06F11/3006 ,  G06F11/3017 ,  G06F11/3024 ,  G06F11/3058 ,  H05K7/20836 ,  Y02D10/16

摘要： A multiprocessor computer system continues operation after the failure of a cooling device coupled to a central processing unit (CPU). In accordance with the present invention, an impending failure of a cooling device is detected, and all user and operating system processes are moved from the affected CPU coupled to the failing cooling device to one or more other CPUs. The system state is then altered so that interrupts are no longer received and processed by the affected CPU, and all memory caches associated with the affected CPU are flushed back to main memory to ensure cache coherency. At this point, the CPU is either powered-down, or placed in a low-power mode that allows the CPU to operate without the cooling device, while the processes that were removed from the suspended CPU continue executing on other CPUs. After the cooling device has been replaced and is operating normally, the CPU can be powered back up, interrupts can be enabled, and the CPU can once again execute user and operating system processes.

摘要翻译： 在与中央处理单元（CPU）耦合的冷却装置发生故障之后，多处理器计算机系统继续运行。 根据本发明，检测到冷却装置的即将发生的故障，并且将所有用户和操作系统处理从耦合到故障冷却装置的受影响的CPU移动到一个或多个其他CPU。 然后更改系统状态，以便受影响的CPU不再接收和处理中断，并且与受影响的CPU相关联的所有内存缓存都将刷新到主内存，以确保高速缓存一致性。 此时，CPU处于掉电状态或置于低功耗模式，允许CPU在没有冷却设备的情况下运行，而从中止CPU中删除的进程在其他CPU上继续执行。 在冷却装置更换并正常运行后，CPU可以重新上电，中断可以启用，CPU可以再次执行用户和操作系统进程。

公开(公告)号：US06574710B1

公开(公告)日：2003-06-03

申请号：US09629128

申请日：2000-07-31

申请人： Blaine D. Gaither ,  Russ W Herrell

发明人： Blaine D. Gaither ,  Russ W Herrell

IPC分类号： G06F1200

CPC分类号： G06F12/0811 ,  G06F12/0831

摘要： A lower level cache detects when a line of memory has been evicted from a higher level cache. The lower level cache stores the address of the evicted line. When the system bus is idle, the lower level cache initiates a transaction causing all higher level caches to invalidate the line. The lower level cache then places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed.

摘要翻译： 较低级别的缓存检测何时一行内存已从较高级别的缓存中逐出。 下级缓存存储被驱逐行的地址。 当系统总线空闲时，较低级别的缓存启动一个事务，导致所有较高级别的缓存使该行无效。 然后，较低级别的缓存将该行置于特殊状态。 如果特殊状态的行从较低级缓存中逐出，则较低级别的缓存知道该行不会在较高级别缓存，因此不需要后退无效事务。

公开(公告)号：US06532151B2

公开(公告)日：2003-03-11

申请号：US09775164

申请日：2001-01-31

申请人： Benjamin D. Osecky ,  Blaine D. Gaither

发明人： Benjamin D. Osecky ,  Blaine D. Gaither

IPC分类号： H05K720

CPC分类号： G06F11/004 ,  G06F1/206 ,  G06F11/20 ,  H05K7/20836

摘要： An obstruction is removed from a computer system cooling fan by manipulating fan rotation. When a fan obstruction is detected, the fan is stopped. If the obstruction is caused by an object that was drawn toward the fan intake, such as a sheet of paper, this operation may clear the obstruction. The fan may also be reversed to attempt to blow the obstruction clear of the fan. Thereafter, the fan is returned to normal operation and is monitored to determine whether the obstruction was removed. If the fan is still obstructed, these steps can be repeated. If the attempts to clear the obstruction are unsuccessful, then the computer system operator or management software can be signaled.

公开(公告)号：US06360301B1

公开(公告)日：2002-03-19

申请号：US09290430

申请日：1999-04-13

申请人： Blaine D Gaither ,  Eric M Rentschler

发明人： Blaine D Gaither ,  Eric M Rentschler

IPC分类号： G06F1212

CPC分类号： G06F12/0811

摘要： A lower level cache detects when a line of memory has been evicted from a higher level cache. The cache coherency protocol for the lower level cache places the line into a special state. If a line in the special state is evicted from the lower level cache, the lower level cache knows that the line is not cached at a higher level, and therefore a back-invalidate transaction is not needed. Reducing the number of back-invalidate transactions improves the performance of the system.

摘要翻译： 较低级别的缓存检测何时一行内存已从较高级别的缓存中逐出。 低级缓存的缓存一致性协议将该行置于特殊状态。 如果特殊状态的行从较低级缓存中逐出，则较低级别的缓存知道该行不会在较高级别缓存，因此不需要后退无效事务。 减少反向无效事务的数量改善了系统的性能。

公开(公告)号：US5915114A

公开(公告)日：1999-06-22

申请号：US799950

申请日：1997-02-14

申请人： Bret A. McKee ,  Blaine D. Gaither

发明人： Bret A. McKee ,  Blaine D. Gaither

IPC分类号： G06F9/45 ,  G06F11/34 ,  G06F11/00

CPC分类号： G06F8/443 ,  G06F11/3466 ,  G06F2201/865

摘要： A dynamic trace-driven object code optimizer provides for dynamic, real-time optimization of executable object code. The dynamic trace-driven object code optimizer bases the real-time optimization of executable object code on data gathered from execution traces collected in real-time. The executable code is then modified in real-time to generate optimized object code that is able to run more quickly and efficiently on the current system.

摘要翻译： 动态跟踪驱动的对象代码优化器提供可执行对象代码的动态，实时优化。 动态跟踪驱动的对象代码优化器将可执行对象代码的实时优化基于从实时收集的执行跟踪收集的数据。 然后可执行代码实时修改，以生成能够在当前系统上更快更有效地运行的优化目标代码。