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公开(公告)号：US10816589B2
公开(公告)日：2020-10-27
申请号：US16474943
申请日：2017-12-26
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Xiaobing Ren , Qun Liu
IPC: G01R31/02 , G01R31/26 , H01L23/544
Abstract: A structure for testing a semiconductor device. A first resistor structure (R1) comprises a first active region (110) and a first polysilicon gate (130) disposed on the first active region (110); the width of the first active region (110) is greater than a predetermined width value; the predetermined width value is the critical value of the width of an active region of the semiconductor device when the step height of a shallow trench isolation structure of the semiconductor device affects the width of a polysilicon gate; the design width of the first polysilicon gate (130) is identical to that of the polysilicon gate of the semiconductor device; a second resistor structure (R2) is connected to the first resistor structure (R1) according to a predetermined circuit structure to form a test circuit, and comprises a second active region (210) and a second polysilicon gate (230) disposed on the second active region (210); the width of the second active region (210) is less than the predetermined width value; the design size of the second polysilicon gate (230) is identical to that of the first polysilicon gate (130); the total resistance of a branch circuit where the second resistor structure (R2) is located is equal to the total resistance of a branch circuit where the first resistor structure (R1) is located.
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公开(公告)号：US10815122B2
公开(公告)日：2020-10-27
申请号：US16305119
申请日：2017-05-26
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Yonggang Hu
Abstract: A MEMS microphone comprises a substrate (110), a lower electrode layer (120), a sacrificial layer (130), a stress layer (140), and an upper electrode layer (150). The substrate (110) is centrally provided with a first opening (111), and the lower electrode layer (120) stretches across the substrate (110). The sacrificial layer (130), the stress layer (140), and the upper electrode layer (150) are sequentially laminated on the lower electrode layer (120), and a second opening (160) is provided on the sacrificial layer (130) and the stress layer (140). The second opening (160) is provided in correspondence with the first opening (111). A stress direction of the stress layer (140) is reverse to a warpage direction of the substrate (110).
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公开(公告)号：US20200335607A1
公开(公告)日：2020-10-22
申请号：US16768563
申请日：2018-11-21
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Shikang CHENG , Yan GU , Sen ZHANG
Abstract: A manufacturing method for a semiconductor device, and an integrated semiconductor device. The manufacturing method comprises: on a semiconductor substrate, forming an epitaxial layer having a first region, a second region, and a third region; forming at least one groove in the third region, forming at least two second doping deep traps in the first region, and forming at least two second doping deep traps in the second region; forming a first dielectric island between the second doping deep traps and forming a second dielectric island on the second doping deep traps; forming a first doping groove at both sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; forming an isolated first doping source region using the second dielectric island as a mask.
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公开(公告)号：US20200216307A1
公开(公告)日：2020-07-09
申请号：US16628001
申请日：2018-07-03
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Dan Dai , Changfeng Xia , Juanjuan Dong
Abstract: A method for manufacturing a dual-cavity structure and a dual-cavity structure, including: etching on a semiconductor substrate to form a first trench array, tops of the first trench array being separated from each other and bottoms thereof being communicated with each other to form a first cavity; growing a first epitaxial layer on the semiconductor substrate on which the first trench array is formed, to cover the first trench array by the first epitaxial layer; etching on the first epitaxial layer to form a second trench array; tops of the second trench array being separated from each other and bottoms thereof being communicated with each other to form a second cavity; growing a second epitaxial layer on the first epitaxial layer on which the second trench array is formed; and etching the first epitaxial layer and the second epitaxial layer to form a straight groove.
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公开(公告)号：US10566990B2
公开(公告)日：2020-02-18
申请号：US16344734
申请日：2017-11-03
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Chuan Luo
Abstract: A segmented resistor string type digital to analog converter comprises: a most significant bit (MSB) resistor string (104) comprising a high level resistor string, an intermediate level resistor string and a ground level resistor string; a decoding circuit (101), configured to decode an n-bit code of the MSB resistor string (104) and output 2n decoded codes; a logic sequential generation circuit (102), connected to the decoding circuit (101) and configured to perform a logic operation on a middle-position code among the 2n decoded codes and a refresh clock signal in non-overlapping sequences, and output two groups of control signals with completely complementary high level durations; a control signal bootstrap circuit (103), connected to the logic sequential generation circuit (102) and configured to perform bootstrap processing on the control signal, and increase the high level of the control signal to a sum of a power supply voltage and a threshold voltage; and a first switch group (106), connected to the control signal bootstrap circuit (103) and the intermediate level resistor string, where on/off of the first switch group (106) is controlled by the control signal after the bootstrap processing, so as to connect the intermediate level resistor string to the circuit or disconnect the intermediate level resistor string from the circuit.
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Patent Agency Ranking
公开(公告)号：US20200005980A1
公开(公告)日：2020-01-02
申请号：US16481600
申请日：2018-07-03
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Congying DONG
IPC: H01F17/00 , H01L23/522
Abstract: A stacked spiral inductor, comprising: a substrate, and multiple stacked insulating layers and inductive metal layers formed on the substrate by means of a semiconductor process. Each inductive metal layer comprises a conductive coil in a shape of a spiral and a through hole area used for connecting two adjacent inductive metal layers. The conductive coils of the inductive metal layers have a common coil center. In two adjacent inductive metal layers, the conductive coil of the lower inductive metal layer is retracted toward the coil center with respect to the conductive coil of the upper inductive metal layer.
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公开(公告)号：US10466065B2
公开(公告)日：2019-11-05
申请号：US15321958
申请日：2015-06-26
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Huagang Wu
IPC: G01C25/00 , G01C19/56 , G01C19/5776
Abstract: A method for correcting the driving amplitude of a gyro sensor, mainly comprises adjusting the size of a driving signal (a preset amplitude value) through feedback of a sensor response amplitude signal (an average amplitude value) in a resonance maintaining time period, so that the response amplitude of the resonance maintaining time period tends to be equal, and a stable resonance amplitude is maintained. Also provided is a system for correcting the driving amplitude of a gyro sensor.
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68.发明申请公开(公告)号：US20190252537A1
公开(公告)日：2019-08-15
申请号：US16329413
申请日：2017-08-31
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Yan GU , Shikang CHENG , Sen ZHANG
IPC: H01L29/78 , H01L27/098 , H01L29/66
CPC classification number: H01L29/7803 , H01L27/02 , H01L27/06 , H01L27/098 , H01L29/06 , H01L29/66712
Abstract: A device integrated with a junction field-effect transistor, the device is divided into a JFET region and a power device area, and the device includes: a drain (201) having a first conduction type; and a first conduction type region (214) disposed on a front face of the drain; the JFET region further includes: a JFET source (208) having a first conduction type; a first well (202) having a second conduction type; a metal electrode (212) formed on the JFET source (208), which is in contact with the JFET source (208); a JFET metal gate (213) disposed on the first well (202) at both sides of the JFET source (208); and a first clamping region (210) located below the JFET metal gate (213) and within the first well (202).
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公开(公告)号：US20190238122A1
公开(公告)日：2019-08-01
申请号：US16312345
申请日：2017-06-21
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Xueyan WANG , Qiang CHEN
Abstract: A ring voltage control oscillator includes: a conversion unit (100), cascaded multistage delay units (200) and cascaded multistage isolation buffer units (300). The conversion unit (100) receives a voltage signal controlled by the external, converts the voltage signal into a current signal and respectively transmits the current signal to a plurality of delay units (200) and a plurality of isolation buffer units (300). The delay unit (200) comprises two signal input terminals and two signal output terminals; the isolation buffer unit (300) comprises two signal input terminals and two signal output terminals; a first signal input terminal and a second signal input terminal of the isolation buffer unit (300) are correspondingly connected to a first signal output terminal and a second signal output terminal of the same stage of the delay unit (200), respectively; clock signals outputted by first signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference; clock signals outputted by the second signal output terminals of two adjacent stages of the isolation buffering units (300) have the same phase difference.
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公开(公告)号：US20190214983A1
公开(公告)日：2019-07-11
申请号：US16328402
申请日：2017-08-22
Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.
Inventor： Chuan LUO
IPC: H03K17/687
CPC classification number: H03K17/6872 , H03K17/00
Abstract: A clock voltage step-up circuit comprises a first inverter, a second inverter, a third inverter, a PMOS transistor, and a bootstrap capacitor. An input end of the first inverter is used for inputting a first clock signal. An input end of the second inverter is connected to an output end of the first inverter, and an output end of the second inverter outputs a first control signal used for controlling a sampling switch; and after the first control signal passes through a fourth inverter, a fifth inverter and a sixth inverter, a second control signal used for controlling the sampling switch is generated. An input end of the third inverter is connected to a second clock signal, and the first clock signals and the second clock signals are a set of clock signals, every two of which are not overlapped. A gate end of the PMOS transistor is connected to a drain end of the PMOS transistor, and a source end of the PMOS transistor is used for being connected to a power supply. One end of the bootstrap capacitor is connected to an output end of the third inverter, and the other end of the bootstrap capacitor is connected to the drain end of the PMOS transistor and is connected to the second inverter, so as to step up a voltage of the first control signal.
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