公开(公告)号：US20150236134A1

公开(公告)日：2015-08-20

申请号：US14412237

申请日：2012-07-18

Applicant: Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Chao Zhao

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/268 ,  H01L21/76283 ,  H01L29/665 ,  H01L29/785

Abstract: A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.

Abstract translation: 提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。 沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域 半导体鳍片延伸。 随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源极/漏极区域接触。 本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

公开(公告)号：US08748983B2

公开(公告)日：2014-06-10

申请号：US13380828

申请日：2011-08-12

Applicant: Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

Inventor： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC: H01L27/12 ,  H01L21/70

CPC classification number: H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.

Abstract translation: 提供一种嵌入式源极/漏极MOS晶体管及其形成方法。 嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。 本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

公开(公告)号：US08685851B2

公开(公告)日：2014-04-01

申请号：US13139063

申请日：2011-01-27

Applicant: Chao Zhao ,  Wenwu Wang

Inventor： Chao Zhao ,  Wenwu Wang

IPC: H01L21/4763 ,  H01L23/48

CPC classification number: H01L27/101 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L27/2436 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function. The method provides a processing which has high controllability and improves the performance of devices.

Abstract translation: 提供具有记忆功能的MOS器件的制造方法，其包括：提供半导体衬底，半导体衬底的表面被第一介电层覆盖，金属互连结构形成在第一介电层中; 形成覆盖在所述第一电介质层和所述金属互连结构的表面上的第二电介质层; 在所述第二介电层中形成开口，所述开口的底部露出所述金属互连结构; 在开口的底部形成合金层，含有铜等金属的合金层的材料; 对合金层和金属互连结构进行热处理，在金属互连结构的表面形成含有氧元素的化合物层。 包含氧元素的化合物层和形成在半导体衬底中的MOS器件构成具有记忆功能的MOS器件。 该方法提供了具有高可控性和提高设备性能的处理。

公开(公告)号：US08575019B2

公开(公告)日：2013-11-05

申请号：US13143507

申请日：2011-02-17

Applicant: Chao Zhao

Inventor： Chao Zhao

IPC: H01L23/535

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a method for forming a metal interlayer via, comprising: forming a seed layer on a first dielectric layer and a first metal layer embedded in the first dielectric layer; forming a mask pattern on the seed layer to expose a portion of the seed layer covering some of the first metal layer; growing a second metal layer on the exposed portion of the seed layer; removing the mask pattern and a portion of the seed layer carrying the mask pattern to expose side walls of the second metal layer, a portion of the first metal layer and the first dielectric layer; forming an insulating barrier layer on the side walls, the portion of the first metal layer and the first dielectric layer. There is also provided a method for forming a metal interconnection line. Both of them can suppress the occurrence of voids. There is further provided a metal interconnection structure comprising a contact plug, a via and a metal interconnection line, wherein the via is formed on the metal interconnection line, the metal gate and/or the contact plug.

Abstract translation: 提供一种用于形成金属中间层通孔的方法，包括：在第一电介质层上形成晶种层和嵌入第一介电层中的第一金属层; 在种子层上形成掩模图案以暴露覆盖一些第一金属层的种子层的一部分; 在种子层的暴露部分上生长第二金属层; 去除掩模图案和承载掩模图案的种子层的一部分以暴露第二金属层的侧壁，第一金属层和第一介电层的一部分; 在侧壁上形成绝缘阻挡层，第一金属层和第一介电层的部分。 还提供了一种用于形成金属互连线的方法。 他们都可以抑制空洞的发生。 还提供了一种金属互连结构，其包括接触插塞，通孔和金属互连线，其中通孔形成在金属互连线，金属栅极和/或接触插塞上。

公开(公告)号：US20130249012A1

公开(公告)日：2013-09-26

申请号：US13640733

申请日：2012-04-11

Applicant: Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

Inventor： Qiuxia Xu ,  Chao Zhao ,  Gaobo Xu

IPC: H01L27/092 ,  H01L21/265

CPC classification number: H04L21/02 ,  H01L21/265 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843

Abstract: This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process.

Abstract translation: 本发明公开了一种CMOS器件，其包括：第一MOSFET; 与第一MOSFET的类型不同的第二MOSFET; 覆盖所述第一MOSFET并具有第一应力的第一应力层; 以及覆盖所述第二MOSFET的第二应力层，其中所述第二应力层掺杂有离子，并且因此具有不同于所述第一应力的第二应力。 本发明的CMOS器件及其制造方法利用分离离子注入方法实现双重应力衬垫，而不需要通过光刻/光刻技术去除PMOS区域上的拉伸应力层或NMOS区域上的压应力层， 蚀刻，从而简化了工艺并降低了成本，并且同时防止了NMOS区域或PMOS区域上的衬垫中的应力不受由沉积工艺的热处理引起的损伤。

公开(公告)号：US20130240996A1

公开(公告)日：2013-09-19

申请号：US13520611

申请日：2012-04-11

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L21/823857 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833

Abstract: The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer, the work function is close to the valence band (conduction band) edge; each of the second gate stack structures comprises a second gate insulating layer, a modified first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the second work function metal layer comprises implanted work function-regulating doped ions, which are simultaneously diffused to the first work function layer below to regulate the threshold such that the work function of the gate is close to the valence band (conduction band) edge and is opposite the original first work function, to thereby regulate the work function accurately.

Abstract translation: 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在两侧的衬底中的多个源极和漏极区域 所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层 ，第二功函数金属扩散阻挡层和栅极填充层，功函数接近价带（导带）边; 每个第二栅极堆叠结构包括第二栅极绝缘层，改性的第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，所述第二功函数金属层包括植入功函数调节 掺杂离子，其同时扩散到下面的第一功函数层以调节阈值，使得栅极的功函数接近价带（导带）边缘并与原始第一功函数相反，从而调节 工作功能准确。

公开(公告)号：US20130228893A1

公开(公告)日：2013-09-05

申请号：US13145301

申请日：2011-04-22

Applicant: Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

Inventor： Huicai Zhong ,  Chao Zhao ,  Qingqing Liang

IPC: H01L21/762 ,  H01L29/02

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L29/02

Abstract: A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.

Abstract translation: 提供了沟槽隔离结构及其形成方法。 沟槽隔离结构包括：半导体衬底和形成在半导体衬底的表面上并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。 通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

公开(公告)号：US08496240B1

公开(公告)日：2013-07-30

申请号：US13463546

申请日：2012-05-03

Applicant: Tung-Wen Tu ,  Long-Chao Zhao

Inventor： Tung-Wen Tu ,  Long-Chao Zhao

IPC: B65H3/06

CPC classification number: B65H3/0684 ,  B65H3/34 ,  B65H2402/5155 ,  B65H2801/06 ,  B65H2801/39

Abstract: An automatic document feeder includes an upper cover, a document pick-up module, and a conveying channel. The upper cover has a first hooking element. The document pick-up module is arranged between the upper cover and the conveying channel. In addition, the document pick-up module has a second hooking element. When the automatic document feeder is operated in a standby mode, the document pick-up module is swung to a position near the upper cover and the second hooking element is engaged with the first hooking element, so that the document pick-up module is fixed on the upper cover. Since the document pick-up module is not contacted with the document when the automatic document feeder is operated in the standby mode, the possibility of causing an erroneous action of the document pick-up module will be eliminated.

Abstract translation: 自动送纸器包括上盖，文件拾取模块和输送通道。 上盖具有第一钩件。 文件拾取模块设置在上盖和输送通道之间。 此外，文件拾取模块具有第二钩构件。 当自动进纸器在待机模式下操作时，文档拾取模块摆动到靠近上盖的位置，第二挂钩元件与第一挂钩元件接合，使得文档拾取模块固定 在上盖上。 由于当在待机模式下操作自动送纸器时文档拾取模块未与文档接触，因此将消除导致文档拾取模块错误动作的可能性。

公开(公告)号：US20130105859A1

公开(公告)日：2013-05-02

申请号：US13582432

申请日：2011-11-28

Applicant: Guilei Wang ,  Chunlong Li ,  Chao Zhao

Inventor： Guilei Wang ,  Chunlong Li ,  Chao Zhao

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/28264 ,  H01L21/823807 ,  H01L21/8258 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/51 ,  H01L29/7833

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, an insulating isolation layer formed on the substrate, a first active region layer and a second active region layer formed in the insulating isolation layer, characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability.

Abstract translation: 本发明公开了一种半导体器件，包括：衬底，形成在衬底上的绝缘隔离层，形成在绝缘隔离层中的第一有源区和第二有源区，其特征在于，第一有源区 区域层和/或第二有源区层比衬底高。 根据本发明的半导体器件及其制造方法，使用由与衬底不同的材料形成的有源区，增加沟道区中的载流子迁移率，从而显着改善器件响应速度 设备性能大大提升。 此外，与现有的STI制造方法不同，对于本发明，首先形成STI，然后进行填充以形成有源区，从而避免STI中产生孔的问题，并提高器件的可靠性。

公开(公告)号：US20130061884A1

公开(公告)日：2013-03-14

申请号：US13641874

申请日：2012-03-23

Applicant: Tao Yang ,  Chao Zhao ,  Junfeng Li

Inventor： Tao Yang ,  Chao Zhao ,  Junfeng Li

IPC: B08B3/04

CPC classification number: H01L21/67051

Abstract: A method for cleaning wafer after chemical mechanical planarization that includes placing the wafer in the wafer holder and rotating the wafer holder and the wafer simultaneously, cleaning with chemicals by providing the wafer surface with chemical detergent through the detergent supply cantilever that keeps a certain distance away from the wafer surface, cleaning with deionized water by providing the wafer surface with deionized water through the detergent supply cantilever to remove the chemical detergent and cleaning products. The method also includes the second clean for better cleaning effect and drying the wafer out. According to the wafer cleaning method, the non-contact detergent and deionized water supply cantilever used for wafer cleaning reduces or eliminates the possible problems in making macro scratches on wafer surface in the scrubbing process and increases the yield for wafer devices.

Abstract translation: 一种用于在化学机械平面化之后清洁晶片的方法，包括将晶片放置在晶片保持器中并同时旋转晶片保持器和晶片，用化学药剂清洗通过在一定距离之外的洗涤剂供给悬臂的化学清洁剂 从晶片表面，用去离子水清洗，通过提供晶片表面的去离子水通过洗涤剂供应悬臂来去除化学清洁剂和清洁产品。 该方法还包括第二次清洁以获得更好的清洁效果并干燥晶片。 根据晶片清洗方法，用于晶片清洗的非接触式洗涤剂和去离子水供应悬臂减少或消除了在洗涤过程中在晶片表面上产生宏观划痕的可能问题，并提高了晶片装置的产量。