公开(公告)号：US5589409A

公开(公告)日：1996-12-31

申请号：US393647

申请日：1995-02-24

Applicant: Constantin Bulucea ,  Michael J. Grubisich

Inventor： Constantin Bulucea ,  Michael J. Grubisich

IPC: H01L21/331 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  Y10S148/01

Abstract: A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with a pair of more lightly doped base portions that encroach substantially into the intrinsic base below the main intrinsic base portion. The two deep encroaching base portions extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced. Manufacture of the transistor entails introducing suitable dopants into a semiconductor body. In one fabrication process, a fast-diffusing dopant is employed in forming the deep encroaching base portions without significantly affecting earlier-created transistor regions.

Abstract translation: 利用特殊的二维本征基极掺杂分布来改善其本征基极包括主本征部分的垂直双极晶体管的输出电流 - 电压特性。 特殊的掺杂分布通过一对更轻掺杂的基底部分实现，其基本上侵入主本征基底部下方的本征基底。 两个深侵入基部分彼此充分地相互延伸，以建立通常提高穿通电压幅度的二维电荷共享机构。 从而提高了晶体管的电流 - 电压特性。 晶体管的制造需要将合适的掺杂剂引入半导体本体。 在一个制造工艺中，快速扩散掺杂剂用于形成深入侵基底部分，而不会明显影响早期产生的晶体管区域。

公开(公告)号：US5581115A

公开(公告)日：1996-12-03

申请号：US319759

申请日：1994-10-07

Applicant: Michael J. Grubisich ,  Constantin Bulucea

Inventor： Michael J. Grubisich ,  Constantin Bulucea

IPC: H01L21/331 ,  H01L29/08 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70

CPC classification number: H01L29/66272 ,  H01L29/0804 ,  H01L29/0821 ,  Y10S148/01

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract translation: 垂直双极晶体管的发射极和基极的一部分与场隔离区相邻以形成壁 - 发射极结构。 该晶体管在集电极和任选地在基极中具有额外的掺杂。 沿着本征基底下方的集电极 - 基极结提供额外的集电极掺杂，以产生与场隔离区域横向分开的特殊集电区。 特殊收集器区域的存在导致本征基极更薄，从而提高截止频率和总体电流增益。 沿着场隔离区域在本征基极中提供额外的基极掺杂以提高晶体管的击穿电压和漏电流特性。

公开(公告)号：US5548158A

公开(公告)日：1996-08-20

申请号：US300498

申请日：1994-09-02

Applicant: Constantin Bulucea ,  Michael J. Grubisich

Inventor： Constantin Bulucea ,  Michael J. Grubisich

IPC: H01L21/331 ,  H01L29/10 ,  H01L27/082 ,  H01L27/102 ,  H01L29/00

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  Y10S148/01

Abstract: A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with a pair of more lightly doped base portions that encroach substantially into the intrinsic base below the main intrinsic base portion. The two deep encroaching base portions extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced.

Abstract translation: 利用特殊的二维本征基极掺杂分布来改善其本征基极包括主本征部分的垂直双极晶体管的输出电流 - 电压特性。 特殊的掺杂分布通过一对更轻掺杂的基底部分实现，其基本上侵入主本征基底部下方的本征基底。 两个深侵入基部分彼此充分地相互延伸，以建立通常提高穿通电压幅度的二维电荷共享机构。 从而提高了晶体管的电流 - 电压特性。

公开(公告)号：US5410170A

公开(公告)日：1995-04-25

申请号：US47723

申请日：1993-04-14

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0696 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/7802

Abstract: Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well.

Abstract translation: 公开了两个拓扑不同的单元，其减少了每个器件的总触点数，并且适用于中高压DMOS晶体管。 这些细胞使用源和身体之间的集成连接，使得它们对于通过颗粒污染或光刻缺陷接触接触不那么敏感。 这些拓扑结构包括细长的六角形细胞或埋深体细胞。 两个电池在高电流中压沟槽DMOS晶体管中是最有效的，其中身体接触的密度变得过高，而周边/面积几何因子不太重要。 所公开的实施例是DMOS结构的沟槽类型。 然而，这些单元也可以在平面DMOS晶体管中实现。

公开(公告)号：US08513703B2

公开(公告)日：2013-08-20

申请号：US12908514

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L21/338 ,  H01L29/778

CPC classification number: H01L29/0661 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.

Abstract translation: 组III-N HEMT的Si衬底形成为限定将Si衬底的上部区域与Si衬底的下部区域电隔离的p-n结的层。 结果，Si衬底的上部区域可以电浮动，从而获得全缓冲击穿电压，而Si衬底的下部区域可以通过导电环氧树脂附着到封装上，从而显着提高导热性 的III-N HEMT组，并且使不期望的浮动电压区域最小化。

公开(公告)号：US20130015535A1

公开(公告)日：2013-01-17

申请号：US13348577

申请日：2012-01-11

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea ,  Sandeep R. Bahl

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea ,  Sandeep R. Bahl

IPC: H01L29/78

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659

Abstract: An asymmetric insulated-gate field effect transistor (100U or 102U) provided along an upper surface of a semiconductor body contains first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima (316-1-316-3) at respective locations (PH-1-PH-3) spaced apart from one another. The tailoring is typically implemented so that the vertical dopant profile of the pocket portion is relatively flat near the upper semiconductor surface. As a result, the transistor has reduced leakage current.

Abstract translation: 沿着半导体主体的上表面设置的非对称绝缘栅场效应晶体管（100U或102U）包含由沟道区（244或284）横向隔开的第一和第二源/漏区（240和242或280和282） 的晶体管的主体材料。 栅电极（262或302）覆盖在沟道区上方的栅介电层（260或300）。 比主体材料的横向相邻材料更重掺杂的主体材料的口袋部分（250或290）在很大程度上仅延伸到第一个S / D区域并进入通道区域。 口袋部分的垂直掺杂剂轮廓被调整为在彼此间隔开的相应位置（PH-1-PH-3）处达到多个局部最大值（316-1-316-3）。 通常实施定制，使得袋部分的垂直掺杂剂分布在上半导体表面附近相对平坦。 结果，晶体管具有减小的漏电流。

公开(公告)号：US20120299097A1

公开(公告)日：2012-11-29

申请号：US13177552

申请日：2011-07-06

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的物体 - 物质位置之前至少增加10倍，不超过上部的10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。

公开(公告)号：US08309420B1

公开(公告)日：2012-11-13

申请号：US13195833

申请日：2011-08-01

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/88

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top of the well. Each well is defined by a corresponding body-material region (108 or 308) of a selected conductivity type. The regions respectively meet overlying zones (104 and 304) of the opposite conductivity type. The concentration of the well dopant reaches a maximum in each body-material region no more than 10 times deeper below the upper semiconductor surface than the overlying zone's depth, decreases by at least a factor of 10 in moving from the empty-well maximum-concentration location through the overlying zone to the upper semiconductor surface, and increases, or decreases by less than a factor of 10, in moving from the filled-well maximum-concentration location through the other zone to the upper semiconductor surface.

Abstract translation: 半导体结构设置有（i）在井的顶部附近具有相对少的阱掺杂物的空阱，以及（ii）在阱的顶部附近具有相当好的掺杂剂的填充阱。 每个孔由所选择的导电类型的对应的主体材料区域（108或308）限定。 这些区域分别满足相反导电类型的覆盖区域（104和304）。 在上半导体表面以上的深层中，阱体掺杂物的浓度达到最大值，在上半导体表面的深度以上10倍以下，在空孔最大浓度的移动中，至少10倍 通过覆盖区域到上半导体表面的位置，并且从填充井最大浓度位置通过另一区域移动到上半导体表面时增加或减小小于10倍。

公开(公告)号：US20120273880A1

公开(公告)日：2012-11-01

申请号：US12912612

申请日：2010-10-26

Applicant: Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

Inventor： Chih Sieh Teng ,  Constantin Bulucea ,  Chin-Miin Shyu ,  Fu-Cheng Wang ,  Prasad Chaparala

IPC: H01L27/088 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 μm deep into the body material but not more than 0.1 μm deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

公开(公告)号：US20120264263A1

公开(公告)日：2012-10-18

申请号：US13293096

申请日：2011-11-09

Applicant: Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

Inventor： Constantin Bulucea ,  William D. French ,  Donald M. Archer ,  Jeng-Jiun Yang ,  Sandeep R. Bahl ,  D. Courtney Parker

IPC: H01L21/8238

CPC classification number: H01L29/1083 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

Abstract: A group of high-performance like-polarity insulated-gate field-effect transistors (100, 108, 112, 116, 120, and 124 or 102, 110, 114, 118, 122, and 126) have selectably different configurations of lateral source/drain extensions, halo pockets, and gate dielectric thicknesses suitable for a semiconductor fabrication platform that provides a wide variety of transistors for analog and/or digital applications. Each transistor has a pair of source/drain zones, a gate dielectric layer, and a gate electrode. Each source/drain zone includes a main portion and a more lightly doped lateral extension. The lateral extension of one of the source/drain zones of one of the transistors is more heavily doped or/and extends less deeply below the upper semiconductor surface than the lateral extension of one of the source/drain zones of another of the transistors.

Abstract translation: 一组高性能类似极性的绝缘栅场效应晶体管（100,108,112,116,120和124或102,110,114,118,122和126）具有可选择地不同的侧向源 /漏极延伸，光晕口和栅介质厚度，适用于为模拟和/或数字应用提供各种晶体管的半导体制造平台。 每个晶体管具有一对源极/漏极区，栅极介电层和栅电极。 每个源极/漏极区域包括主要部分和更轻掺杂的横向延伸部分。 一个晶体管的一个源极/漏极区域的横向延伸比另一个晶体管的源极/漏极区域之一的横向延伸更深地掺杂或/并且在上部半导体表面之下更深地延伸。