公开(公告)号：US11527528B2

公开(公告)日：2022-12-13

申请号：US16853777

申请日：2020-04-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jie Zeng ,  Raunak Kumar

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/762 ,  H01L29/165

Abstract: An electrostatic discharge (ESD) protection device may be provided, including a substrate having a conductivity region arranged therein, a first terminal region and a second terminal region arranged within the conductivity region, and a field distribution structure. The field distribution structure may include an intermediate region arranged within the conductivity region between the first terminal region and the second terminal region, an isolation element arranged over the intermediate region, and a first conductive plate and a second conductive plate arranged over the isolation element. The first conductive plate may be electrically connected to the first terminal region and the second conductive plate may be electrically connected to the second terminal region.

公开(公告)号：US11513175B2

公开(公告)日：2022-11-29

申请号：US16787226

申请日：2020-02-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping Zheng ,  Eng Huat Toh ,  Kazutaka Yamane ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L27/22 ,  G01R33/09 ,  H01L43/02 ,  H01F41/34 ,  H01F10/32 ,  H01L43/12

Abstract: A semiconductor device may be provided including a first series portion and a second series portion electrically connected in parallel with the first series portion. The first series portion may include a first MTJ stack and a first resistive element electrically connected in series. The second series portion may include a second MTJ stack and a second resistive element electrically connected in series. The first resistive element may include a third MTJ stack and the second resistive element may include a fourth MTJ stack. The first, second, third, and fourth MTJ stacks may include a same number of layers, which may include a fixed layer, a free layer, and a tunnelling barrier layer between the fixed layer and the free layer. Alternatively, the first resistive element may include a first transistor and the second resistive element may include a second transistor.

公开(公告)号：US20220344470A1

公开(公告)日：2022-10-27

申请号：US17238755

申请日：2021-04-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kyongjin HWANG ,  Raunak KUMAR ,  Robert J. GAUTHIER, JR.

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) devices and methods of manufacture. The structure includes a bipolar transistor device, including a base region, having a base contact region, in a first well of a first conductivity type, a collector region, having a collector contact region, in a second well of a second conductivity type, and an emitter region, having an emitter contact region, in the first well, located between the base contact region and the second well, and a reverse-doped resistance well, of the second conductivity type, located in the first well of the first conductivity type between the base contact region and the emitter contact region structured to decrease turn-on voltage of the bipolar transistor device.

公开(公告)号：US11469169B2

公开(公告)日：2022-10-11

申请号：US17100950

申请日：2020-11-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bong Woong Mun ,  Jeoung Mo Koo

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

Abstract: A capacitor is provided. The capacitor includes a first conductive layer in a first isolation region in a substrate and a plurality of dielectric layers over the first isolation region. The plurality of dielectric layers may include inter layer dielectric (ILD) and inter metal dielectric (IMD) layers. The first conductive layer is a bottom plate of the capacitor. A second conductive layer is arranged over the plurality of dielectric layers, whereby the second conductive layer is a top plate of the capacitor and at least partially overlaps with the first conductive layer.

公开(公告)号：US11456306B2

公开(公告)日：2022-09-27

申请号：US17100954

申请日：2020-11-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bong Woong Mun ,  Jeoung Mo Koo

IPC: H01L27/11521 ,  H01L49/02 ,  H01L29/06 ,  H01L29/788 ,  H01L29/66

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.

公开(公告)号：US11444168B2

公开(公告)日：2022-09-13

申请号：US17086501

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jiacheng Lei ,  James Jerry Joseph ,  Khee Yong Lim ,  Lulu Peng ,  Lawrence Selvaraj Susai

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778 ,  H01L29/10

Abstract: A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.

公开(公告)号：US11380677B2

公开(公告)日：2022-07-05

申请号：US16860087

申请日：2020-04-28

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jiacheng Lei ,  Lawrence Selvaraj Susai

IPC: H01L29/778 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L21/8252 ,  H01L29/66 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/872

Abstract: According to various embodiments, a transistor device may include a semiconductor structure having a trench formed therein. The semiconductor structure may include a buffer layer and a barrier layer arranged over the buffer layer. The trench may extend at least to the buffer layer. The transistor device may include a source terminal, a drain terminal, and a gate terminal arranged between the source terminal and the drain terminal. The gate terminal may extend into the trench. The transistor device may include an electrode component. The electrode component may include an electrode. The electrode component may extend into the trench where the electrode component is separated from the gate terminal. The electrode component may contact a side wall of the trench.

公开(公告)号：US20220205948A1

公开(公告)日：2022-06-30

申请号：US17699219

申请日：2022-03-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang WANG ,  Bin LIU ,  Eng Huat TOH ,  Shyue Seng TAN ,  Kiok Boone Elgin QUEK

IPC: G01N27/414 ,  H01L29/16 ,  H01L29/04

Abstract: According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.

公开(公告)号：US11374135B2

公开(公告)日：2022-06-28

申请号：US16556333

申请日：2019-08-30

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Shyue Seng Tan ,  Eng Huat Toh

IPC: H01L31/02 ,  H01L31/028 ,  H01L31/18 ,  H01L31/0392 ,  H01L31/107 ,  H01L31/0312

Abstract: A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.

公开(公告)号：US11372061B2

公开(公告)日：2022-06-28

申请号：US16817623

申请日：2020-03-13

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yongshun Sun ,  Eng Huat Toh ,  Ping Zheng

IPC: G01R33/07 ,  G01R33/00 ,  H01L43/14 ,  H01L43/06 ,  H01L43/04

Abstract: A Hall effect sensor device may be provided, including one or more sensor structures. Each sensor structure may include: a base layer having a first conductivity type; a Hall plate region having a second conductivity type opposite from the first conductivity type arranged above the base layer; a first isolating region arranged around and adjoining the Hall plate region, and contacting the base layer; a plurality of second isolating regions arranged within the Hall plate region; and a plurality of terminal regions arranged within the Hall plate region. The first and second isolating regions may include electrically insulating material, and each neighboring pair of terminal regions may be electrically isolated from each other by one of the second isolating regions.