公开(公告)号：US08134871B2

公开(公告)日：2012-03-13

申请号：US12536127

申请日：2009-08-05

申请人： Deepanshu Dutta ,  Henry Chin

发明人： Deepanshu Dutta ,  Henry Chin

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.

摘要翻译： 根据其WLn-1相邻存储元件的状态，通过在分离的组中对所选字线WLn上的存储元件进行编程来对非易失性存储系统中的程序干扰进行减少，并且对于每一个，向WLn-1施加最佳的通过电压 组。 最初，读取WLn-1上的存储元件的状态。 程序迭代包括多个程序脉冲。 当向WLn-1施加第一通过电压时，将第一编程脉冲施加到WLn，选择第一组WLn存储元件进行编程，并且禁止第二组WLn存储元件。 接下来，向WLn施加第二编程脉冲，同时将第二通过电压施加到WLn-1，选择第二组WLn存储元件进行编程，并且禁止第一组WLn存储元件。 组可以包括一个或多个数据状态。

公开(公告)号：US20110252283A1

公开(公告)日：2011-10-13

申请号：US13164401

申请日：2011-06-20

申请人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

IPC分类号： G06F11/25

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

摘要翻译： 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果解码失败，则从存储器读取软数据位。 在接收到硬读取结果之后和在软位操作的每个阶段提供初始可靠性度量值。 在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。 当在比较级的第二子集读取时，可以基于第一子集数据执行解码。

公开(公告)号：US20110235428A1

公开(公告)日：2011-09-29

申请号：US13151938

申请日：2011-06-02

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C16/10

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。

公开(公告)号：US07975209B2

公开(公告)日：2011-07-05

申请号：US11694950

申请日：2007-03-31

申请人： Henry Chin ,  Nima Mokhlesi

发明人： Henry Chin ,  Nima Mokhlesi

IPC分类号： H03M13/00

CPC分类号： G06F12/0246 ,  G06F2212/7209 ,  H03M13/1102

摘要： Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed to. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

摘要翻译： 使用迭代概率解码对非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，将初始可靠性度量（诸如对数似然比）用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 可以执行使用基于数据中的误差水平的可调节温度参数的模拟退火。 模拟退火可以将随机性作为噪声引入到解码过程中。 此外，可以使用器件特性的知识来引导模拟退火过程，而不是引入绝对随机性。 引入一定程度的随机性增加了灵活性，允许在数据可能不可纠正的情况下可能更快的收敛时间和收敛。

公开(公告)号：US20100009503A1

公开(公告)日：2010-01-14

申请号：US12170321

申请日：2008-07-09

申请人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

发明人： James K. Kai ,  Dana Lee ,  Takashi Whitney Orimoto ,  Vinod R. Purayath ,  George Matamis ,  Henry Chin

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： A method of fabricating a memory system is disclosed that includes a set of non-volatile storage elements. The method includes forming a floating gate having a top and at least two sides. A dielectric cap is formed at the top of the floating gate. An inter-gate dielectric layer is formed around the at least two sides of the floating gate and over the top of the dielectric cap. A control gate is formed over the top of the floating gate, the inter-gate dielectric layer separates the control gate from the floating gate. In one aspect, forming the dielectric cap includes implanting oxygen in the top of the floating gate and heating the floating gate to form the dielectric cap from the implanted oxygen and silicon from which the floating gate was formed.

摘要翻译： 公开了一种制造存储器系统的方法，其包括一组非易失性存储元件。 该方法包括形成具有顶部和至少两个侧面的浮动栅极。 在浮动栅极的顶部形成介电盖。 在浮栅的至少两侧并且在电介质盖的顶部之上形成栅极间电介质层。 控制栅极形成在浮置栅极的顶部之上，栅极间介质层将控制栅极与浮动栅极分离。 在一个方面，形成电介质盖包括在浮置栅极的顶部注入氧并且加热浮动栅极以从形成浮栅的注入的氧和硅形成电介质盖。

公开(公告)号：US20080250300A1

公开(公告)日：2008-10-09

申请号：US11693649

申请日：2007-03-29

申请人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

IPC分类号： G11C7/10 ,  H03M13/00

CPC分类号： G06F12/00 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/028 ,  H03M13/11 ,  H03M13/37

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. In another approach, the initial reliability metrics are based on multiple reads. Tables which store the reliability metrics and adjustments based on the sensed states can be prepared before decoding occurs.

摘要翻译： 使用迭代概率解码和多次读取操作来解码存储在非易失性存储器中的数据，以实现更高的可靠性。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的读取数据。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果没有发生收敛，例如在设定的时间周期内，再次感测到非易失性存储元件的状态，则调整解码器中的可靠性度量的当前值，并且解码再次尝试收敛。 在另一种方法中，初始可靠性度量是基于多次读取。 可以在解码发生之前准备存储基于感测状态的可靠性度量和调整的表。

公开(公告)号：US20080244360A1

公开(公告)日：2008-10-02

申请号：US11694948

申请日：2007-03-31

申请人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

IPC分类号： H03M13/03

CPC分类号： H03M13/1111 ,  G06F11/1068 ,  G11C11/5642 ,  H03M13/1102

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

摘要翻译： 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果解码失败，则从存储器读取软数据位。 在接收到硬读取结果之后和在软位操作的每个阶段提供初始可靠性度量值。 在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。 当在比较级的第二子集读取时，可以基于第一子集数据执行解码。

公开(公告)号：US06667929B1

公开(公告)日：2003-12-23

申请号：US10171863

申请日：2002-06-14

申请人： Vesselina K. Zaharinova-Papazova ,  William W. Shen ,  Henry Chin

发明人： Vesselina K. Zaharinova-Papazova ,  William W. Shen ,  Henry Chin

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2211/4061

摘要： Apparatus for limiting the power consumption of a random access memory (RAM), having in combination a counter for counting the number of memory commands in a sample interval, and power governor control logic responsive to the number of memory commands, for limiting the maximum number of transfer requests processed in a sample interval when the counter accumulates a count exceeding a predetermined value.

摘要翻译： 用于限制随机存取存储器（RAM）的功耗的装置，其组合有用于对采样间隔中的存储器命令的数量进行计数的计数器和响应于存储器命令数量的功率调节器控制逻辑，用于限制最大数量 当计数器累积超过预定值的计数时，在采样间隔中处理的传送请求。

公开(公告)号：US5787486A

公开(公告)日：1998-07-28

申请号：US572987

申请日：1995-12-15

申请人： Henry Chin ,  John Edward Derrick ,  Christopher Michael Herring ,  George Totolos, Jr.

发明人： Henry Chin ,  John Edward Derrick ,  Christopher Michael Herring ,  George Totolos, Jr.

IPC分类号： G06F9/46 ,  G06F12/08 ,  G06F12/14

CPC分类号： G06F9/52 ,  G06F12/0888

摘要： An apparatus and method are provided for maintaining lock characteristics while providing selective access to a cache during lock cycles. To guarantee that only one master accesses memory at a time, locked cycles are always passed to the internal arbitration unit of the memory controller, even if they are cache hits. If the local bus is not granted or cannot be guaranteed that it will be granted the bus for the locked cycle, the cycle is cancelled.

摘要翻译： 提供了一种用于在锁定周期期间保持锁定特性同时提供对高速缓存的选择性访问的装置和方法。 为了保证只有一个主机一次访问存储器，即使是高速缓存命中，锁存周期也总是传递给存储器控制器的内部仲裁单元。 如果本地总线未被授予或不能保证将被授予该锁定周期的总线，该周期将被取消。

公开(公告)号：USD366655S

公开(公告)日：1996-01-30

申请号：US31814

申请日：1994-12-06

申请人： Russell Sanchez ,  Mike Paull ,  Steve Kaneko ,  Henry Chin ,  Robert Dillon ,  Michael Knodt ,  Claire Beliard

设计人： Russell Sanchez ,  Mike Paull ,  Steve Kaneko ,  Henry Chin ,  Robert Dillon ,  Michael Knodt ,  Claire Beliard