公开(公告)号：US20240418772A1

公开(公告)日：2024-12-19

申请号：US18820651

申请日：2024-08-30

Applicant: ROHM CO., LTD.

Inventor： Takashi FUJIMURA ,  Takashi KIRA

IPC: G01R31/28 ,  G01R31/00 ,  G06F1/06 ,  H03K21/02 ,  H03K21/10

Abstract: A monitoring circuit includes first and second oscillators, first and second frequency dividers, first and second counters, a determination portion, and an identification portion. The first and second frequency dividers respectively divide frequencies of first and second clock signals outputted from the first and second oscillators, respectively. The first and second counters respectively count the numbers of clocks of the second and first clock signals at first and second numbers of periods of first and second frequency-divided signals outputted from the first and second frequency dividers, respectively. The determination portion determines, based on results of counting by the first and second counters, whether or not an abnormality has occurred in either of the first and second clock signals. The identification portion identifies, at the occurrence of an abnormality in either of the first and second clock signals, which of the first and second clock signals is in an abnormal state.

公开(公告)号：US12168262B2

公开(公告)日：2024-12-17

申请号：US17267595

申请日：2019-08-23

Applicant: ROHM CO., LTD.

Inventor： Kazunori Fuji

IPC: B23K26/082 ,  B23K26/21 ,  H01L23/00

Abstract: A joint structure includes a first and a second metal member overlapping with each other as viewed in a first direction. The first metal member and the second metal member are joined together. The joint structure includes a welded portion at which the first metal member and the second metal member, overlapping with each other, are partly fused to each other. The welded portion has an outer circumferential edge and a plurality of linear marks. The outer circumferential edge is annular as viewed in the first direction. The plurality of linear marks each extend from an inside of the welded portion toward the outer circumferential edge as viewed in the first direction. Each of the plurality of linear marks is curved to bulge to one sense of an annular direction along the outer circumferential edge.

公开(公告)号：US20240405772A1

公开(公告)日：2024-12-05

申请号：US18805727

申请日：2024-08-15

Applicant: ROHM CO., LTD.

Inventor： Yosuke YAMANAKA ,  Yuji SHIMADA ,  Koji SAITO

IPC: H03K17/691

Abstract: For example, a pulse transmission circuit includes: a constant current source configured to generate a constant current; a capacitor configured to be charged using the constant current (e.g., a charge current generated by mirroring the constant current); and a discharge switch configured to pass a discharge current from the capacitor to a transformer according to a pulse edge in an input pulse signal, thereby to pulse-drive the transformer.

公开(公告)号：US20240405770A1

公开(公告)日：2024-12-05

申请号：US18798965

申请日：2024-08-09

Applicant: ROHM CO., LTD.

Inventor： Kiminobu SATO

IPC: H03K17/687 ,  B60R16/033

Abstract: A driving control device for controlling the driving of the gate of a cut-off NMOS transistor arranged to be connectable between a first power supply circuit and a second power supply circuit includes a boost circuit configured to feed a gate control voltage to the gate and a controller configured, in start-up control for the cut-off NMOS transistor, to keep the current capacity of the boost circuit during start-up at a first current capacity and, after that, to switch the current capacity of the boost circuit to a second current capacity higher than the first current capacity.

公开(公告)号：US20240405665A1

公开(公告)日：2024-12-05

申请号：US18801943

申请日：2024-08-13

Applicant: ROHM CO., LTD.

Inventor： Kazuhiro HORII

IPC: H02M1/32 ,  H02M1/00 ,  H02M3/335

Abstract: In a calibration step, a search processing unit changes a setting value so as to search for a critical value that corresponds to a boundary that defines whether or not overcurrent protection functions in a state in which a switching power supply apparatus is operated with a current at which overcurrent protection is to function in normal operation of the switching power supply apparatus. In a calibration step, a digital processor writes the setting value based on the critical value searched for by the search processing unit to nonvolatile memory. In the normal startup operation of the switching power supply apparatus, the digital processor reads the setting value from the nonvolatile memory and sets the setting value for the overcurrent detection circuit.

公开(公告)号：US20240405117A1

公开(公告)日：2024-12-05

申请号：US18798932

申请日：2024-08-09

Applicant: ROHM CO., LTD.

Inventor： Hirotaka OTAKE

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

Abstract: A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer containing acceptor impurities, a gate electrode, a passivation layer, a source electrode, a drain electrode, and a field plate electrode. The field plate electrode is located on the passivation layer between the gate layer and the drain electrode. The gate layer includes a ridge where the gate electrode is located, a source-side extension extending from the ridge, and a drain-side extension extending from the ridge to a side opposite to the source-side extension. The passivation layer includes a field plate non-overlapping region that does not overlap the field plate electrode and is located immediately above the drain-side extension.

公开(公告)号：US20240405074A1

公开(公告)日：2024-12-05

申请号：US18797966

申请日：2024-08-08

Applicant: ROHM CO., LTD.

Inventor： Yuji KOGA

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/808

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface at an opposite side thereto, a bottom gate region of a first conductivity type that is formed in the semiconductor layer, and a top gate region of the first conductivity type that is formed in a surface layer portion of the first surface of the semiconductor layer and faces the bottom gate region in a thickness direction of the semiconductor layer, the bottom gate region includes a first bottom gate region at the source region side and a second bottom gate region at the drain region side, and an interval in the thickness direction between the second bottom gate region and the top gate region is greater than an interval in the thickness direction between the first bottom gate region and the top gate region.

公开(公告)号：US20240404977A1

公开(公告)日：2024-12-05

申请号：US18804601

申请日：2024-08-14

Applicant: ROHM CO., LTD.

Inventor： Kazunori FUJI

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L25/065

Abstract: A semiconductor device includes a first semiconductor element with a first gate electrode, a second semiconductor element with a second gate electrode, a sealing resin, a first signal terminal with a third center, and a first signal wiring. The first line connecting the first center of the first gate electrode and the third center has a first line length L1. The second line connecting the second center of the second gate electrode and the third center has a second line length L2. The path from the first center to the third center via the first signal wiring has a first path length R1. The path from the second center to the third center via the first signal wiring has a second path length R2. In the semiconductor device, R2/R1 is closer to 1 than is L2/L1.

公开(公告)号：US20240401229A1

公开(公告)日：2024-12-05

申请号：US18669362

申请日：2024-05-20

Applicant: ROHM CO., LTD.

Inventor： Keiju SATO ,  Makoto TAKAMURA

IPC: C30B25/18 ,  C30B29/02 ,  C30B29/58 ,  C30B29/60 ,  C30B33/02

Abstract: The present disclosure provides a composite substrate. The composite substrate includes: a SiC single crystal substrate having an off-angle; and a carbon-containing layer including a laminate of a reconstructed surface layer and a graphene layer, or a graphene layer disposed in contact with a surface of the SiC single crystal substrate. When an outermost surface of the SiC single crystal substrate is a Si-terminated surface, the laminate is disposed above the SiC single crystal substrate, and the graphene layer of the laminate is one or two layers. When the outermost surface of the SiC single crystal substrate is a C-terminated surface, one or two graphene layers are arranged above the SiC single crystal substrate.

公开(公告)号：US20240400395A1

公开(公告)日：2024-12-05

申请号：US18806177

申请日：2024-08-15

Applicant: ROHM CO., LTD.

Inventor： Keiju SATO

IPC: C01B32/186

Abstract: The method of manufacturing graphene comprises placing a semiconductor substrate on a carbon susceptor, placing a supply member above the carbon susceptor or a semiconductor substrate, heating the supply member and the carbon susceptor by at least one of a first heating source and a second heating source, heating the semiconductor substrate by heating the carbon susceptor, and forming one or more graphene layers on the semiconductor substrate.