公开(公告)号：US12160237B2

公开(公告)日：2024-12-03

申请号：US17843693

申请日：2022-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Kailash Kumar ,  Ravinder Kumar

IPC: H03K19/0185 ,  H03K19/003

Abstract: An integrated circuit includes an output pad, and I/O driver that drives data to the output pad, and a predriver that controls the I/O driver. The integrated circuit includes maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs to the predriver a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage.

公开(公告)号：US20240395924A1

公开(公告)日：2024-11-28

申请号：US18662577

申请日：2024-05-13

Applicant: STMicroelectronics International N.V.

Inventor： Salvatore CASCINO ,  Mario Giuseppe SAGGIO ,  Mario PULVIRENTI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

Abstract: An electronic device includes a semiconductor body of SiC having an upper surface and a lower surface opposite to each other along a first axis and including: a drain substrate extending into the semiconductor body starting from the bottom surface and with a first electrical conductivity type; a drift layer extending into the semiconductor body starting from the upper surface and with the first electrical conductivity type and a second dopant concentration; a body region accommodated in the drift layer; and a source region accommodated in the body region. The electronic device further includes a gate structure on the upper surface. The semiconductor body further comprises at least one doped pocket region which is buried in the drift layer, has a second electrical conductivity type and is aligned along the first axis with the source region and/or with the gate structure.

公开(公告)号：US20240395319A1

公开(公告)日：2024-11-28

申请号：US18791901

申请日：2024-08-01

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

公开(公告)号：US20240393439A1

公开(公告)日：2024-11-28

申请号：US18671527

申请日：2024-05-22

Applicant: STMicroelectronics International N.V.

Inventor： Raul Andres BIANCHI ,  Christel Marie-Noëlle BUJ

IPC: G01S7/481 ,  G01S17/894 ,  H01L27/146

Abstract: The present disclosure relates to a process to control an optoelectronic device comprising a single-photon avalanche diode n a substrate, wherein the diode comprises a first region doped with a first type of conductivity level with a first face of the substrate and a second region doped with a second type of conductivity extending from the first face to a second face of the substrate opposed to the first face, wherein the device comprises a third conducting or semiconducting region at the second face, wherein the process comprises the application of a biasing voltage to the third region in order to generate an electric field that accelerates the charges generated in the diode.

公开(公告)号：US20240387328A1

公开(公告)日：2024-11-21

申请号：US18319132

申请日：2023-05-17

Applicant: STMicroelectronics International N.V.

Inventor： Pascal Fornara ,  Antonin Chollet ,  Julien Amouroux

IPC: H01L23/48 ,  H01L21/764 ,  H01L21/768 ,  H01L29/06

Abstract: A method for manufacturing a semiconductor device includes depositing a first protective layer over a first conductive feature and a second conductive feature. The first protective layer covers respective sidewalls and top surfaces of the first conductive feature and the second conductive feature. A portion of the first protective layer between the first conductive feature and the second conductive feature is removed. After removing the portion of the first protective layer, an intermetal dielectric layer is formed between the first conductive feature and the second conductive feature.

公开(公告)号：US12149241B2

公开(公告)日：2024-11-19

申请号：US18334989

申请日：2023-06-14

Applicant: STMicroelectronics International N.V.

Inventor： Vaibhav Garg ,  Abhishek Jain ,  Anand Kumar

IPC: H03K17/693 ,  H03K17/687 ,  H03K19/017

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

公开(公告)号：US20240377198A1

公开(公告)日：2024-11-14

申请号：US18654869

申请日：2024-05-03

Applicant: STMicroelectronics International N.V.

Inventor： Gabriele GATTERE ,  Luca GUERINONI

IPC: G01C19/5762 ,  G01C19/5726

Abstract: Test method of a vibrational MEMS structure wherein, a direct, variable modification voltage is applied to a resonance modification test structure having non-rectilinear electrodes, modifying the resonance frequency of the movable mass and the driving frequency. During the test, the movable mass is verified about stability and, if not stable, the vibrational MEMS structure is rejected.

公开(公告)号：US20240370382A1

公开(公告)日：2024-11-07

申请号：US18652555

申请日：2024-05-01

Applicant: STMicroelectronics International N.V.

Inventor： Loic Pallardy ,  Vincent Berthelot

IPC: G06F12/14

Abstract: The system on chip includes a memory controller adapted to receive transactions containing transaction information defining an access to a memory, the memory controller being configured to store the transaction information in a command register, and to control the access to the memory from the content of the command register. The memory controller includes verification circuitry configured to determine the access to the memory depending on a comparison between the transaction information stored in the command register and a list of special information defining special transactions.

公开(公告)号：US20240367610A1

公开(公告)日：2024-11-07

申请号：US18774290

申请日：2024-07-16

Applicant: STMicroelectronics International N.V.

Inventor： Subodh Vikram SHUKLA ,  Saurabh SONA

IPC: B60R25/04 ,  G06F21/44 ,  G06F21/60 ,  H02P27/06 ,  H03K17/94 ,  H04B10/80

Abstract: A method of performing an authentication process to authenticate an electric motor unit includes establishing, by an external controller, secure encrypted communication with motor electronics of the electric motor unit, and sending, by the external controller, an authentication request to the motor electronics over the secure encrypted communication. The method further includes receiving, by the external controller, an authentication response from the motor electronics, verifying, by the external controller, a motor of the electronic motor unit as an authorized part based on the authentication response, and enabling control of the motor by the external controller only after successful authentication.

公开(公告)号：US12136917B2

公开(公告)日：2024-11-05

申请号：US18151337

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Kallol Chatterjee ,  Rohit Kumar Gupta

IPC: H03K19/0185

Abstract: Provided is a voltage level shifter that operates in sub-threshold voltages. The level shifter includes a level shifting stage. The level shifting stage receives a first signal from a first voltage domain and outputs a second signal to a second voltage domain. The level shifter includes a first auxiliary stage. In response to the first signal having a first voltage level corresponding to a first logical state and a first node of the level shifting stage having a supply voltage level, the first auxiliary stage sources current to a second node of the level shifting stage. Sourcing the current to the second node accelerates a transition of the first node to a reference voltage. The level shifting stage outputs a second signal to a second voltage domain.