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公开(公告)号：US20230082546A1
公开(公告)日：2023-03-16
申请号：US18049979
申请日：2022-10-26
发明人： Scott Brad Herner
IPC分类号： H01L27/11582 , H01L29/08 , H01L27/11568 , H01L27/11578
摘要： A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.
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公开(公告)号：US20220383953A1
公开(公告)日：2022-12-01
申请号：US17730056
申请日：2022-04-26
发明人： Shohei Kamisaka , Vinod Purayath , Jie Zhou
IPC分类号： G11C16/04 , H01L27/11556 , H01L27/11582 , H01L29/786 , H01L29/66
摘要： A method for forming a three-dimensional memory structure above a semiconductor substrate includes forming two or more active stack sections, each formed on top of each other and separated by a dielectric buffer layer, where each active stack section includes multilayers separated by isolation dielectric layers and trenches with shafts filled with a sacrificial material. After the multiple active stack sections are formed, the method removes the sacrificial material in the shafts and removes portions of the dielectric buffer layer between shafts of adjacent active stack sections. The method fills the openings with a gate dielectric layer and a gate conductor. In some embodiments, the gate dielectric layer is discontinuous in the shaft over the depth of the multiple active stack sections.
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公开(公告)号：US11515432B2
公开(公告)日：2022-11-29
申请号：US17155673
申请日：2021-01-22
IPC分类号： H01L21/8239 , H01L29/792 , H01L27/11568 , H01L29/51 , H01L29/423
摘要： A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.
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公开(公告)号：US11507301B2
公开(公告)日：2022-11-22
申请号：US17176860
申请日：2021-02-16
发明人： Robert D. Norman
IPC分类号： G06F3/06
摘要： A semiconductor memory module for shared memory access implements memory-centric structures using a quasi-volatile memory. In one embodiment, the memory module for shared memory access includes a memory cube providing high capacity memory coupled to multiple multi-port memories to support simultaneous memory access at multiple memory interfaces. In other embodiments, a memory module incorporates a processor to implement computational memory architecture. In some embodiments, a mini core memory system implements a memory architecture for providing direct and parallel memory access to a mini processor core array.
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公开(公告)号：US20220343980A1
公开(公告)日：2022-10-27
申请号：US17723204
申请日：2022-04-18
发明人： Shohei Kamisaka , Vinod Purayath
IPC分类号： G11C16/04 , H01L23/522 , H01L23/528 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/11582
摘要： A process for fabricating a three-dimensional NOR memory string of storage transistors implements a channel-last fabrication process with channel replacement using silicon germanium (SiGe). In particular, the process uses silicon germanium as a sacrificial layer, to be replaced with the channel material after the charge-storage layer of the storage transistors is formed. In this manner, the channel region is prevented from experiencing excessive high-temperature processing steps, such as during the annealing of the charge-storage layer.
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公开(公告)号：US20220328518A1
公开(公告)日：2022-10-13
申请号：US17809535
申请日：2022-06-28
发明人： Scott Brad Herner , Wu-Yi Henry Chien , Jie Zhou , Eli Harari
IPC分类号： H01L27/11582 , H01L29/66 , H01L21/308
摘要： Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.
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67.发明申请公开(公告)号：US20220293623A1
公开(公告)日：2022-09-15
申请号：US17804986
申请日：2022-06-01
发明人： Tianhong Yan , Scott Brad Herner , Jie Zhou , Wu-Yi Henry Chien , Eli Harari
IPC分类号： H01L27/11573 , H01L27/11565 , H01L29/45 , H01L23/528 , H01L21/311 , H01L21/02 , H01L21/3205 , H01L21/225 , H01L29/786 , H01L29/66 , H01L27/11582
摘要： A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
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68.发明申请公开(公告)号：US20220254390A1
公开(公告)日：2022-08-11
申请号：US17666255
申请日：2022-02-07
摘要： A memory module including a memory array of storage transistors and a control circuit where the control circuit includes a memory interface for providing high bandwidth access to the memory array on serial data lanes. In some embodiments, the control circuit of a memory module includes multiple transceivers for connecting to serial data lanes. In one embodiment, the memory interface of a memory module configures some transceivers for host connection or for upstream connection to an upstream memory module and configures other transceivers for downstream connection to a downstream memory module. In other embodiments, a multi-module memory device is formed using multiple memory modules connected in a cascade configuration or in a star configuration to provide high bandwidth memory access to all memory locations of the multiple memory modules using the given number of serial data lanes of the host connection.
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公开(公告)号：US20220199532A1
公开(公告)日：2022-06-23
申请号：US17548034
申请日：2021-12-10
发明人： Shohei Kamisaka , Yosuke Nosho
IPC分类号： H01L23/535 , H01L23/528 , H01L23/532 , H01L21/768
摘要： A conductor-filled via formed between an interconnection conductor layer and a buried contact above a planar surface of a semiconductor substrate, includes: (a) a first portion that extends from the interconnection conductor layer through a first isolation layer to a step in a staircase structure formed above the buried contacts, wherein (i) the step of the staircase structure is aligned to the buried contact along a first direction substantially normal to the planar surface of the semiconductor substrate, (ii) at the top of the step, the step comprises a bit line layer, a source line layer and a second isolation layer between the bit line layer and the source line layer, and (iii) the first portion electrically contacting the layer at the top of the step; and (b) a second portion extending from a portion of the step below the layer at the top of the step to the buried contact, wherein a spacer insulator lines sidewalls of the conductor-filled via.
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公开(公告)号：US20220180943A1
公开(公告)日：2022-06-09
申请号：US17529083
申请日：2021-11-17
发明人： Raul Adrian Cernea
摘要： A semiconductor memory device is implemented as a string of storage transistors with sense amplifier connected drain terminals and floating source terminals. In some embodiments, a method in the semiconductor memory device applies a bit line control (BLC) voltage with a voltage step down to the bias device during the read operation to reduce the settling time on the bit line, thereby shortening the access time for data read out from the storage transistors. In other embodiments, a method in the semiconductor memory device including an array of strings of storage transistors uses a current from a biased but unselected bit line as the sense amplifier reference current for reading stored data from a selected bit line. In one embodiment, the sense amplifier reference current is provided to a referenced sense amplifier to generate a sense amplifier data latch signal.
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