公开(公告)号：US20090187732A1

公开(公告)日：2009-07-23

申请号：US11972715

申请日：2008-01-11

申请人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

发明人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/145 ,  G06F2212/651 ,  G06F2212/652

摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address.

摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和区域第一表，区域秒表，区域第三表或段表中的任何一个的初始起始地址。 基于获得的初始起始地址，获得包含格式控制和DAT保护字段的段表条目。 如果格式控制字段被使能，则从转换表条目获得主存储器中的大块数据的段帧绝对地址。 分段帧绝对地址与虚拟地址的页索引部分和字节索引部分组合，以形成所需数据块的转换地址。 如果DAT保护字段未被使能，则获取和存储被允许被转换的虚拟地址寻址的所需数据块。

公开(公告)号：US20090187728A1

公开(公告)日：2009-07-23

申请号：US11972694

申请日：2008-01-11

申请人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

发明人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

IPC分类号： G06F9/34

CPC分类号： G06F12/1009 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/455 ,  G06F12/1045 ,  G06F12/109 ,  G06F12/1475

摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. A segment table entry obtained from a segment table contains a format control field. If the format control field is enabled, a segment-frame absolute address of a large block of data in main storage is obtained from the segment table entry. Each 4K byte block of data within the large block has an associated storage key. Store operations associated with the virtual address are performed to the desired block of data. If the change recording override field is disabled, the change bit of the storage key associated with the desired 4K byte block is set to 1. An indication is then provided that the desired 4K byte block has been modified.

摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 从段表获得的段表条目包含格式控制字段。 如果启用格式控制字段，则从段表条目获取主存储器中的大块数据的分段帧绝对地址。 大块内的每4K字节的数据块具有关联的存储密钥。 与虚拟地址相关联的存储操作被执行到期望的数据块。 如果改变记录覆盖字段被禁用，则与期望的4K字节块相关联的存储密钥的改变位被设置为1.然后提供所需的4K字节块已被修改的指示。

公开(公告)号：US06662296B1

公开(公告)日：2003-12-09

申请号：US09677231

申请日：2000-10-02

申请人： Mark S. Farrell ,  John S. Liptay ,  Charles F. Webb

发明人： Mark S. Farrell ,  John S. Liptay ,  Charles F. Webb

IPC分类号： G06F926

CPC分类号： G06F9/30094 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/322

摘要： An exemplary embodiment of the present invention is a method and system for reducing the number of branch instructions required to test combinations of millicode branch points. The method is implemented via a pipe-lined computer processor executing a millicode routine. The processor interrogates a millicode condition code; interrogates a first field of the TMBP instruction, the results of which determine a logical function to be performed on the millicode condition code; interrogates a second field of the TMBP instruction which specifies a first millicode branch point; interrogates a third field of the TMBP instruction, which specifies a second millicode branch point; and sets a millicode condition code based upon the results of the interrogating and used for executing subsequent TMBP instructions or conditional branch instructions.

摘要翻译： 本发明的示例性实施例是用于减少测试毫分支点的组合所需的分支指令的数量的方法和系统。 该方法通过执行millicode例程的管道式计算机处理器来实现。 处理器询问一个millicode条件代码; 询问TMBP指令的第一个字段，其结果确定要对毫代数条件代码执行的逻辑功能; 询问指定第一毫分支点的TMB​​P指令的第二字段; 询问TMBP指令的第三个字段，其指定第二个毫分支点; 并根据询问的结果设置一个millicode条件代码，并用于执行后续TMBP指令或条件转移指令。

公开(公告)号：US06490689B1

公开(公告)日：2002-12-03

申请号：US09337157

申请日：1999-06-21

申请人： David Arlen Elko ,  Jeffrey M. Nick ,  Ronald M. Smith, Sr. ,  Charles F. Webb

发明人： David Arlen Elko ,  Jeffrey M. Nick ,  Ronald M. Smith, Sr. ,  Charles F. Webb

IPC分类号： G06F104

CPC分类号： G06F1/14

摘要： A physical clock is expanded to enhance its precision. Existing instructions are capable of using the enhanced physical clock. Execution of an instruction begins, which places a value of the expanded physical clock in a physical clock field of a clock representation. The physical clock field is, however, unable to accommodate the value provided by the expanded physical clock. Thus, that value encroaches upon another predefined field of the clock representation. Completion of the instruction is therefore delayed such that the value provided by the expanded physical clock can be accommodated in the clock representation and a correct value for the another predefined field can be provided.

摘要翻译： 物理时钟被扩展以提高其精度。 现有指令能够使用增强的物理时钟。 开始执行指令，将扩展的物理时钟的值置于时钟表示的物理时钟字段中。 然而，物理时钟字段无法适应扩展的物理时钟提供的值。 因此，该值侵占了时钟表示的另一个预定义字段。 指令的完成因此被延迟，使得扩展的物理时钟提供的值可以被容纳在时钟表示中，并且可以提供另一个预定义字段的正确值。

公开(公告)号：US5568631A

公开(公告)日：1996-10-22

申请号：US466840

申请日：1995-06-06

申请人： Charles F. Webb

发明人： Charles F. Webb

IPC分类号： G06F9/26 ,  G06F9/24

CPC分类号： G06F9/265

摘要： A control store for a microprocessor is divided into two segments with one segment of the control store located on the microprocessor chip and the other segment of the control store located on a separate chip. In multiprocessor applications, a number of the microprocessors share the control store segment on the separate chip. Each control store word includes a field containing a prediction of the address for the next control store word needed by the microprocessor. The predicted address is used to access the control store prior to receipt of the actual request by the processor. When the processor actually requests the next control store word, a compare is performed between the predicted address and the address actually requested by the processor. If they match, the control store word is passed on to the processor. If they do not, the address actually requested by the processor is used to obtain the next control store word. In multiprocessor applications, a number of microprocessors share the same control store segment on the separate chip. As long as the actual address requested by a microprocessor matches the predicted address stored with the previously accessed control store word in the shared segment of the control store, that microprocessor retains access to the shared control store segment. However, on occurrence of a mismatch it loses its priority to access the shared segment and must await the satisfaction of all pending requests of other microprocessors before it can again access the shared segment and obtain the control store word at the actual address requested.

摘要翻译： 用于微处理器的控制存储器被分成两个段，控制存储器的一个段位于微处理器芯片上，控制存储器的另一个段位于单独的芯片上。 在多处理器应用中，许多微处理器在独立的芯片上共享控制存储段。 每个控制存储字包括一个包含微处理器所需的下一个控制存储字的地址预测的字段。 预测地址用于在处理器接收到实际请求之前访问控制存储。 当处理器实际请求下一个控制存储字时，在预测地址和处理器实际请求的地址之间执行比较。 如果它们匹配，则控制存储字被传递到处理器。 如果没有，处理器实际请求的地址用于获取下一个控制存储字。 在多处理器应用中，许多微处理器在独立芯片上共享相同的控制存储段。 只要微处理器请求的实际地址与存储在控制存储器的共享段中的先前访问的控制存储字存储的预测地址匹配，该微处理器保留对共享控制存储段的访问。 然而，在发生不匹配时，它失去访问共享段的优先级，并且必须等待其他微处理器的所有待处理请求的满足，才能再次访问共享段，并在所请求的实际地址处获取控制存储字。

公开(公告)号：US5495590A

公开(公告)日：1996-02-27

申请号：US480107

申请日：1995-06-07

申请人： Steven T. Comfort ,  Clifford O. Hayden ,  John S. Liptay ,  Susan B. Stillman ,  Charles F. Webb

发明人： Steven T. Comfort ,  Clifford O. Hayden ,  John S. Liptay ,  Susan B. Stillman ,  Charles F. Webb

IPC分类号： G06F9/38 ,  G06F11/14

CPC分类号： G06F9/3863 ,  G06F11/1407

摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.

摘要翻译： 一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。 在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。 然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。 因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。

公开(公告)号：US5371867A

公开(公告)日：1994-12-06

申请号：US974393

申请日：1992-11-10

申请人： Jonel George ,  Roger E. Hough ,  Moon J. Kim ,  Allen H. Preston ,  David E. Stucki ,  Charles F. Webb

发明人： Jonel George ,  Roger E. Hough ,  Moon J. Kim ,  Allen H. Preston ,  David E. Stucki ,  Charles F. Webb

IPC分类号： G06F12/06 ,  G06F9/46 ,  G06F12/02 ,  G06F12/10 ,  G06F12/08

CPC分类号： G06F12/10

摘要： Enables a host (hypervisor) to access any location in any guest zone in a large memory, when host and guest operands have small addresses that cannot access locations outside of their own zones. System hardware/microcode provides a particular number of windows for host use. Each CPU in the system has one or more window access registers (WARs), and one or more window registers (WRs). The host uses a load WAR instruction to designate each page frame (PF) in the host zone to be used as a host window, and each PF is associated with a respective window number. When the host receives an interception signal requiring the host to access a guest location represented by a guest zone identifier and a guest small address, the host designates one of its window numbers for an access to this guest location. Then, the host executes an activate WR instruction which invokes CPU hardware/microcode that generates a large absolute address for accessing this guest location in the large memory and stores it in a WR associated with the window number. When the host thereafter executes any instruction with an operand small address accessing the host window PF associated with that WR, and CPU hardware/microcode automatically substitutes that guest large address in the WR for the host operand small address for accessing the guest location.

摘要翻译： 当主机和访客操作数具有不能访问其本身区域之外的位置的小地址时，使主机（管理程序）能够访问大内存中任何访客区域中的任何位置。 系统硬件/微码提供特定数量的主机使用的窗口。 系统中的每个CPU都有一个或多个窗口访问寄存器（WARs）和一个或多个窗口寄存器（WR）。 主机使用加载WAR指令来指定要用作主机窗口的主机区域中的每个页面帧（PF），并且每个PF与相应的窗口编号相关联。 当主机接收到要求主机访问由客户区域标识符和客人小地址表示的客户位置的拦截信号时，主机指定其窗口号码之一用于访问该访客位置。 然后，主机执行一个激活WR指令，该指令调用生成大型绝对地址的CPU硬件/微码，用于访问大存储器中的该客户位置，并将其存储在与窗口号相关联的WR中。 当主机此后执行任何具有访问与该WR相关联的主机窗口PF的操作数小地址的指令，并且CPU硬件/微代码自动地将该客户机大地址替换为用于访问客户位置的主操作数小地址。

公开(公告)号：US5276882A

公开(公告)日：1994-01-04

申请号：US558998

申请日：1990-07-27

申请人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio ,  Charles F. Webb

发明人： Philip G. Emma ,  Joshua W. Knight ,  James H. Pomerene ,  Rudolph N. Rechtschaffen ,  Frank J. Sparacio ,  Charles F. Webb

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4426

摘要： Method and apparatus for correctly predicting an outcome of a branch instruction in a system of the type that includes a Branch History Table (BHT) and branch instructions that implement non-explicit subroutine calls and returns. Entries in the BHT have two additional stage fields including a CALL field to indicate that the branch entry corresponds to a branch that may implement a subroutine call and a PSEUDO field. The PSEUDO field represents linkage information and creates a link between a subroutine entry and a subroutine return. A target address of a successful branch instruction is used to search the BHT. The branch is known to be a subroutine return if a target quadword contains an entry prior to a target halfword that has the CALL field set. The entry with the CALL bit set is thus known to be the corresponding subroutine call, and the entry point to the subroutine is given by the target address stored within the entry. A PSEUDO entry is inserted into the BHT at the location corresponding to the entry point of the subroutine, the PSEUDO entry being designated as such by having the PSEUDO field asserted. The PSEUDO entry contains the address of the returning branch instruction in place of the target address field.

摘要翻译： 用于正确预测包括分支历史表（BHT）的类型的系统中的分支指令的结果和实现非显式子程序调用和返回的分支指令的方法和装置。 BHT中的条目具有两个附加的阶段字段，包括CALL字段，以指示分支条目对应于可以实现子程序调用的分支和PSEUDO字段。 PSEUDO字段表示链接信息，并创建子程序条目和子程序返回之间的链接。 成功的分支指令的目标地址用于搜索BHT。 如果目标四字包含有设置了CALL字段的目标半字之前的条目，则该分支被称为子程序返回。 因此，具有CALL位置位的条目是相应的子程序调用，并且子程序的入口点由存储在条目中的目标地址给出。 将PSEUDO条目插入到与子程序的入口点相对应的位置处的BHT中，PSEUDO条目被指定为通过使PSEUDO字段被断言。 PSEUDO条目包含返回分支指令的地址，代替目标地址字段。

公开(公告)号：US5257354A

公开(公告)日：1993-10-26

申请号：US641987

申请日：1991-01-16

申请人： Steven T. Comfort ,  John S. Liptay ,  Charles F. Webb

发明人： Steven T. Comfort ,  John S. Liptay ,  Charles F. Webb

IPC分类号： G06F9/38 ,  G06F11/28 ,  G06F9/30 ,  G06F11/30

CPC分类号： G06F9/3836 ,  G06F9/3861

摘要： A system whereby a central processor continues operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage. The needed assurance of correct operation is gained by monitoring the storage locations from which fetches are made on behalf of instructions which logically follow the serializing operation, but which are made prior to the time that fetching is allowed to resume. If those storage locations are not changed during the time between when the first such fetch is actually made from one of them, and the time that fetching is allowed to resume, then the results of the processing which was done by the CPU (based on those fetches) must be exactly the same as if all of the fetches and processing was done in a single instant at the moment that the fetches became allowed.

公开(公告)号：USD252151S

公开(公告)日：1979-06-19

申请号：US786604

申请日：1977-04-11

申请人： Charles F. Webb

设计人： Charles F. Webb