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    Processor, method and computer program product for fast selective invalidation of translation lookaside buffer
    3.
    发明授权
    Processor, method and computer program product for fast selective invalidation of translation lookaside buffer 有权
    处理器，方法和计算机程序产品，用于快速选择性地无效翻译后备缓冲区

    公开(公告)号：US08112174B2

    公开(公告)日：2012-02-07

    申请号：US12036398

    申请日：2008-02-25

    申请人： Jonathan T. Hsieh ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    发明人： Jonathan T. Hsieh ,  Chung-Lung Kevin Shum ,  Charles F. Webb

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027

    摘要： A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided.

    摘要翻译： 一种处理器，包括适于使至少一个逻辑地址映射至少一个绝对地址无效的微体系结构，包括：至少一个翻译后备缓冲器（TLB）及其多个副本; 独立索引TLB每份副本的逻辑; 多个比较器，每个比较器与每个TLB端口的每个TLB组输出的相应输出相关联，其中每个比较器适于识别无效化的映射; 以及使每个识别的映射无效的逻辑。 提供了一种方法和计算机程序产品。

    OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE
    4.
    发明申请
    OPERAND FETCHING CONTROL AS A FUNCTION OF BRANCH CONFIDENCE 有权
    操作控制作为分支机构的功能

    公开(公告)号：US20110320774A1

    公开(公告)日：2011-12-29

    申请号：US12822379

    申请日：2010-06-24

    申请人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    发明人： Christian Jacobi ,  Barry W. Krumm ,  Brian R. Prasky ,  Martin Recktenwald ,  Chung-Lung K. Shum ,  Charles F. Webb ,  Joshua M. Weinberg

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F9/3806 ,  G06F9/3844 ,  G06F9/3857

    摘要： A system for data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.

    摘要翻译： 一种用于数据操作数取出控制的系统包括一计算机处理器，该计算机处理器包括用于确定存储器访问操作的控制 控制单元被配置为执行方法。 该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。 该方法还包括将尝试访问系统存储器的所选择的指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。 该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

    System, method and computer program product for translating storage elements
    5.
    发明授权
    System, method and computer program product for translating storage elements 有权
    用于翻译存储元件的系统，方法和计算机程序产品

    公开(公告)号：US07966474B2

    公开(公告)日：2011-06-21

    申请号：US12036520

    申请日：2008-02-25

    申请人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

    发明人： Chung-Lung Kevin Shum ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Bruce C Giamei ,  Bernd Nerz ,  David A. Schroter ,  Charles F. Webb

    IPC分类号： G06F9/26

    CPC分类号： G06F9/3017 ,  G06F9/30018 ,  G06F9/30101 ,  G06F9/355

    摘要： A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

    摘要翻译： 一种用于计算机系统中的翻译的系统，方法和计算机程序产品。 该系统包括包含地址转换表的基地址的通用寄存器。 该系统还包括被配置为接收多个要被翻译的元件的毫代可访问特殊位移寄存器。 该系统还包括多路复用器，用于从毫代可访问特殊位移寄存器中选择多个元件中的特定元件，并用于产生位移或偏移值。 该系统还包括地址发生器，用于创建包含来自通用寄存器的基地址和所生成的位移或偏移值的组合地址。

    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS
    7.
    发明申请
    METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING FILTERING OF GUEST2 QUIESCE REQUESTS 失效
    方法，系统和计算机程序产品，用于提供GUEST2 QUIESCE要求的过滤

    公开(公告)号：US20090217264A1

    公开(公告)日：2009-08-27

    申请号：US12037887

    申请日：2008-02-26

    申请人： Lisa C. Heller ,  Damian L. Osisek ,  Charles F. Webb

    发明人： Lisa C. Heller ,  Damian L. Osisek ,  Charles F. Webb

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45558 ,  G06F2009/45566

    摘要： A method, system and computer program product for providing filtering of level two guest (G2) quiesce requests. The method includes receiving a G2 quiesce interruption request at a processor currently or previously executing a G2 running under a level two hypervisor in a logical partition. The G2 includes a current zone and G2 virtual machine (VM) identifier. The quiesce interruption request specifies an initiating zone and an initiating G2 VM identifier. It is determined if the G2 quiesce interruption request can be filtered by the processor. The determining is responsive to the current G2 VM identifier, the current zone, the initiating zone and the initiating G2 VM identifier. The G2 quiesce interruption request is filtered at the processor in response to determining that the G2 quiesce interruption request can be filtered. Thus, filtering between G2 virtual machines running in the logical partition is provided.

    摘要翻译： 一种用于提供二级客户（G2）静默请求过滤的方法，系统和计算机程序产品。 该方法包括在当前或先前执行在逻辑分区中的二级虚拟机管理程序下运行的G2的处理器处接收G2停顿中断请求。 G2包括当前区域和G2虚拟机（VM）标识符。 静默中断请求指定启动区域和启动G2 VM标识符。 确定G2停顿中断请求是否可以被处理器过滤。 该确定响应于当前的G2 VM标识符，当前区域，起始区域和起始G2 VM标识符。 响应于确定可以过滤G2静默中断请求，在处理器处对G2静默中断请求进行过滤。 因此，提供了在逻辑分区中运行的G2虚拟机之间的过滤。

    Method and system for managing the result from a translator co-processor in a pipelined processor
    8.
    发明授权
    Method and system for managing the result from a translator co-processor in a pipelined processor 有权
    用于管理流水线处理器中的翻译协处理器的结果的方法和系统

    公开(公告)号：US06671793B1

    公开(公告)日：2003-12-30

    申请号：US09678061

    申请日：2000-10-02

    申请人： Scott B. Swaney ,  Mark S. Farrell ,  John D. MacDougall ,  Hans-Juergen Muenster ,  Charles F. Webb

    发明人： Scott B. Swaney ,  Mark S. Farrell ,  John D. MacDougall ,  Hans-Juergen Muenster ,  Charles F. Webb

    IPC分类号： G06F1516

    CPC分类号： G06F9/3017 ,  G06F9/3842 ,  G06F9/3861 ,  G06F9/3863 ,  G06F9/3879

    摘要： An exemplary embodiment of the invention is a method and system for managing a result returned from a translator co-processor to a recovery unit of a central processor. The computer system has a pipelined computer processor and a pipelined central processor, which executes an instruction set in a hardware controlled execution unit and executes an instruction set in a milli-mode architected state with a millicode sequence of instructions in the hardware controlled execution unit. The central processor initiates a request to the translator co-processor a cycle after decode of a perform translator operation instruction in the millicode sequence. The translator co-processor processes the perform translator operation instruction to generate a perform translator operation result. The translator co-processor returns the results to a recovery unit of the central processor. The recovery unit stores the perform translator operation result in a system register. The request for the perform translator operation result by the central processor is interlocked by a hardware interlock of the recovery unit until the translator co-processor returns the perform translator operation result. The mechanism allows the recovery unit to maintain the correct perform translator operation result with speculative execution and instruction level retry recovery throughout the duration of the perform translator operation.

    摘要翻译： 本发明的示例性实施例是用于管理从翻译器协处理器返回到中央处理器的恢复单元的结果的方法和系统。 计算机系统具有流水线计算机处理器和流水线中央处理器，其执行硬件控制执行单元中的指令集，并且在硬模式执行单元中以毫列指令序列执行毫模式架构状态指令集。 中央处理器在解码执行转换器操作指令之后的一个循环中向转译器协处理器发出一个请求。 翻译协处理器处理执行翻译器操作指令以产生执行转换器操作结果。 翻译协处理器将结果返回到中央处理器的恢复单元。 恢复单元将执行转换器操作结果存储在系统寄存器中。 由中央处理器执行的执行转换器操作结果的请求由恢复单元的硬件互锁互锁，直到转换器协处理器返回执行转换器操作结果。 该机制允许恢复单元在执行转换器操作的整个持续时间内通过推测执行和指令级重试恢复来维持正确的执行转换器操作结果。

    Specialized millicode instruction for range checking
    9.
    发明授权
    Specialized millicode instruction for range checking 失效
    专用millicode指令进行范围检查

    公开(公告)号：US5621909A

    公开(公告)日：1997-04-15

    申请号：US614148

    申请日：1996-03-12

    申请人： Charles F. Webb ,  Mark S. Farrell ,  Wen H. Li

    发明人： Charles F. Webb ,  Mark S. Farrell ,  Wen H. Li

    IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/00

    CPC分类号： G06F9/30021 ,  G06F9/30094

    摘要： A range check instruction sequence, which performs a logical comparison between two 32-bit values and updates the condition code as a result. It operates identically to the ESA/390 instruction compare logical (CLR) except for the way in which the condition code is set. The new condition code is a function of both the comparison result and the previous condition code. If the first operand is greater than the second operand, the condition code remains unchanged. If the first operand is less than or equal to the second operand, the condition code is set to 2 if it was previously 0 or 1, and is set to 3 if it was previously 2 or 3. This may be understood as advancing the state of the condition code among the groups (0,1), 2, and 3 if the first operand is not greater than the second operand.

    摘要翻译： 范围检查指令序列，其执行两个32位值之间的逻辑比较，并作为结果更新条件代码。 除了条件码的设置方式以外，它与ESA / 390指令比较逻辑（CLR）相同。 新条件代码是比较结果和先前条件代码的函数。 如果第一个操作数大于第二个操作数，则条件代码保持不变。 如果第一个操作数小于或等于第二个操作数，则如果先前为0或1，则条件代码设置为2，如果先前为2或3，则将其设置为3。这可以被理解为推进状态 如果第一个操作数不大于第二个操作数，组（0,1），2和3中的条件代码。

    Method for processing checkpoint instructions to allow concurrent execution of overlapping instructions
    10.
    发明授权
    Method for processing checkpoint instructions to allow concurrent execution of overlapping instructions 失效
    用于处理检查点指令以允许并发执行重叠指令的方法

    公开(公告)号：US5495587A

    公开(公告)日：1996-02-27

    申请号：US263497

    申请日：1994-06-21

    申请人： Steven T. Comfort ,  Clifford O. Hayden ,  John S. Liptay ,  Susan B. Stillman ,  Charles F. Webb

    发明人： Steven T. Comfort ,  Clifford O. Hayden ,  John S. Liptay ,  Susan B. Stillman ,  Charles F. Webb

    IPC分类号： G06F9/38 ,  G06F11/14

    CPC分类号： G06F9/3863 ,  G06F11/1407

    摘要： An instruction processing system and method which utilizes instruction completion to isolate errors, including those in the post-completion processing of operand stores, to an interval between checkpoints, while allowing the processing of checkpointing instructions to be overlapped with that of other instructions. Checkpoints are established before and after such instructions, and all processing (including that of operand stores) from before a checkpoint must be done prior to allowing instruction completion to move beyond the checkpoint. Nevertheless, instructions from beyond a checkpoint are allowed to be processed up to the point of completion while waiting for the checkpoint to be cleared. The point at which instructions must wait on a prior checkpoint is thus moved to the final phase of instruction processing (instruction completion), at significant performance advantage over a conventional implementation in which this waiting is done at instruction fetch, decode, or execution time.

    摘要翻译： 一种指令处理系统和方法，其使用指令完成将包括操作数存储器的后完成处理中的错误的错误隔离到检查点之间的间隔，同时允许检查点指令的处理与其他指令的处理重叠。 在这些指令之前和之后建立检查点，并且必须在允许指令完成超出检查点之前完成检查点之前的所有处理（包括操作数存储的处理）。 然而，在等待检查点被清除之前，允许超出检查点的指令被处理到完成点。 因此，相对于在指令获取，解码或执行时间完成这种等待的常规实现，指令必须在先前检查点上等待的点被移动到指令处理（指令完成）的最后阶段。