公开(公告)号：US07745277B2

公开(公告)日：2010-06-29

申请号：US11065061

申请日：2005-02-25

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/7849

摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor layer on a substrate. The first region of the substrate is expanded to push up the first portion of the semiconductor layer, thereby applying tensile stress to the first portion. The second region of the substrate is compressed to pull down the second portion of the semiconductor layer, thereby applying compressive stress to the second portion. An N type device is formed over the first portion of the semiconductor layer, and a P type device is formed over the second portion of the semiconductor layer.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成半导体层。 衬底的第一区域被膨胀以向上推动半导体层的第一部分，从而对第一部分施加拉伸应力。 衬底的第二区域被压缩以拉下半导体层的第二部分，从而向第二部分施加压应力。 在半导体层的第一部分上形成N型器件，并且在半导体层的第二部分上形成P型器件。

公开(公告)号：US07595247B2

公开(公告)日：2009-09-29

申请号：US11753862

申请日：2007-05-25

申请人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

摘要： Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.

摘要翻译： 通过在栅极再氧化步骤后立即进行晕圈注入，可获得对超薄绝缘体上的场效应晶体管（UTSOI-FET）的短沟道效应的优异控制。 然后形成偏移，然后执行延伸注入工艺。 这个处理步骤的顺序确保了晕轮植入物与延伸植入物横向分离偏移间隔物的宽度。 与传统的UTSOI-FET相比，这种结构产生等效或远优于短沟道性能。 另外，与常规方法相比，上述处理步骤允许使用较低的光晕剂量。

公开(公告)号：US20080290409A1

公开(公告)日：2008-11-27

申请号：US11753862

申请日：2007-05-25

申请人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

发明人： Omer H. Dokumaci ,  John M. Hergenrother ,  Shreesh Narasimha ,  Jeffrey W. Sleight

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78696

摘要： Superior control of short-channel effects for an ultra-thin semiconductor-on-insulator field effect transistor (UTSOI-FET) is obtained by performing a halo implantation immediately after a gate reoxidation step. An offset is then formed and thereafter an extension implantation process is performed. This sequence of processing steps ensures that the halo implant is laterally separated from the extension implant by the width of the offset spacer. This construction produces equivalent or far superior short channel performance compared to conventional UTSOI-FETs. Additionally, the above processing steps permit the use of lower halo doses as compared to conventional processes.

摘要翻译： 通过在栅极再氧化步骤后立即进行晕圈注入，可获得对超薄绝缘体上的场效应晶体管（UTSOI-FET）的短沟道效应的优异控制。 然后形成偏移，然后执行延伸注入工艺。 这个处理步骤的顺序确保了晕轮植入物与延伸植入物横向分离偏移间隔物的宽度。 与传统的UTSOI-FET相比，这种结构产生等效或远优于短沟道性能。 另外，与常规方法相比，上述处理步骤允许使用较低的光晕剂量。

公开(公告)号：US20080230840A1

公开(公告)日：2008-09-25

申请号：US12132705

申请日：2008-06-04

申请人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

发明人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

IPC分类号： H01L49/00

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

公开(公告)号：US07402870B2

公开(公告)日：2008-07-22

申请号：US10711899

申请日：2004-10-12

申请人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

发明人： Huajie Chen ,  Omer H. Dokumaci ,  Oleg G. Gluschenkov ,  Werner A. Rausch

IPC分类号： H01L29/76

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅​​衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

公开(公告)号：US20080128861A1

公开(公告)日：2008-06-05

申请号：US11555906

申请日：2006-11-02

申请人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

发明人： Omer H. Dokumaci ,  Gregory G. Freeman ,  Marwan H. Khater ,  Rajendran Krishnasamy ,  Kathryn T. Schonenberg

IPC分类号： H01L29/73

CPC分类号： H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

摘要： Methods of boosting the performance of bipolar transistor, especially SiGe heterojunction bipolar transistors, is provided together with the structure that is formed by the inventive methods. The methods include providing a species-rich dopant region comprising C, a noble gas, or mixtures thereof into at least a collector. The species-rich dopant region forms a perimeter or donut-shaped dopant region around a center portion of the collector. A first conductivity type dopant is then implanted into the center portion of the collector to form a first conductivity type dopant region that is laterally constrained, i.e., confined, by the outer species-rich dopant region.

摘要翻译： 提供双极晶体管，特别是SiGe异质结双极晶体管的性能的方法与通过本发明方法形成的结构一起提供。 所述方法包括向至少一个收集器提供包含C，惰性气体或其混合物的富含物质的掺杂剂区域。 富含物质的掺杂剂区域围绕收集器的中心部分形成周边或环形掺杂剂区域。 然后将第一导电型掺杂剂注入到集电极的中心部分中，以形成由外部富物质掺杂区域横向约束，即限制的第一导电型掺杂剂区域。

公开(公告)号：US07345329B2

公开(公告)日：2008-03-18

申请号：US11057129

申请日：2005-02-15

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L31/112

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/1054 ,  H01L29/6656

摘要： The first source and drain regions are formed in an upper surface of a SiGe substrate. The first source and drain regions containing an N type impurity. Vacancy concentration in the first source and drain regions are reduced in order to reduce diffusion of the N type impurity contained in the first source and drain regions. The vacancy concentration is reduced by an interstitial element or a vacancy-trapping element in the first source and drain regions. The interstitial element or the vacancy-trapping element is provided by ion-implantation.

摘要翻译： 第一源区和漏区形成在SiGe衬底的上表面中。 含有N型杂质的第一源区和漏区。 为了减少包含在第一源极和漏极区域中的N型杂质的扩散，第一源区和漏区中的空位浓度被降低。 空位浓度通过第一源极和漏极区域中的间隙元素或空穴捕获元件而减小。 间隙元素或空位捕获元件通过离子注入提供。

公开(公告)号：US07091563B2

公开(公告)日：2006-08-15

申请号：US11057126

申请日：2005-02-15

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci

IPC分类号： H01L27/092

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/84

摘要： A method for manufacturing an integrated circuit that has a plurality of semiconductor devices including an n-type field effect transistor and a p-type field effect transistor. This method involves depositing oxide fill on the n-type transistor and the p-type transistor and chemical/mechanical polishing the deposited oxide fill such that a gate stack of the n-type transistor and a gate stack of the p-type transistor, which each have spacers which are surrounded with oxide. The method further involves etching a portion of the polysilicon from a gate of the p-type field effect transistor, depositing a low resistance material (e.g., Co, Ni, Ti, or other similar metals) on the n-type field effect transistor and the p-type field effect transistor, and heating the integrated circuit such that the deposited material reacts with the polysilicon of the n-type transistor and the polysilicon of the p-type transistor to form silicide. The silicide formed on the p-type polysilicon imposes compressive mechanical stresses along the longitudinal direction of the channel of the p-type field effect transistor. A semiconductor device formed by this method has compressive stresses along the length of the PFET channel and tensile stresses along the length of the NFET channel.

摘要翻译： 一种具有包括n型场效应晶体管和p型场效应晶体管的多个半导体器件的集成电路的制造方法。 该方法包括在n型晶体管和p型晶体管上沉积氧化物填充物，并化学/机械抛光沉积的氧化物填充物，使得n型晶体管的栅极堆叠和p型晶体管的栅极堆叠，其中 每个具有被氧化物包围的间隔物。 该方法还包括从p型场效应晶体管的栅极蚀刻多晶硅的一部分，在n型场效应晶体管上沉积低电阻材料（例如，Co，Ni，Ti或其它类似的金属），以及 p型场效应晶体管，并且加热集成电路，使得沉积的材料与n型晶体管的多晶硅和p型晶体管的多晶硅反应以形成硅化物。 形成在p型多晶硅上的硅化物沿着p型场效应晶体管的沟道的纵向施加压缩机械应力。 通过该方法形成的半导体器件具有沿着PFET沟道的长度的压缩应力和沿着NFET沟道的长度的拉伸应力。

公开(公告)号：US07041538B2

公开(公告)日：2006-05-09

申请号：US10713971

申请日：2003-11-14

申请人： Meikei Ieong ,  Omer H. Dokumaci ,  Thomas S. Kanarsky ,  Victor Ku

发明人： Meikei Ieong ,  Omer H. Dokumaci ,  Thomas S. Kanarsky ,  Victor Ku

IPC分类号： H01L21/00

CPC分类号： H01L29/78696 ,  H01L29/456 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78621

摘要： A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.

摘要翻译： 一种高性能凹陷沟道CMOS器件，包括具有凹陷沟道区域和相邻的延伸注入区域和可选的晕轮植入区域的SOI层; 并且提供存在于SOI层顶上的至少一个栅极区域及其制造方法。 邻接的延伸部分和可选的晕轮植入区域具有突然的侧向轮廓并且位于所述栅极区域下方。

公开(公告)号：US07037818B2

公开(公告)日：2006-05-02

申请号：US10711080

申请日：2004-08-20

申请人： Omer H. Dokumaci ,  Xinlin Wang ,  Huilong Zhu

发明人： Omer H. Dokumaci ,  Xinlin Wang ,  Huilong Zhu

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7834 ,  H01L21/26586 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628

摘要： A structure, apparatus and method for improving the performance of semiconductor devices is provided. The semiconductor structure includes a raised source/drain region above a planar source/drain. The raised source/drain has at least a first step and a second step with a variety of transitions therebetween. The first step is of a prescribed height configured to optimize performance of the semiconductor device and is arranged next to a gate. The first step has a top surface above a lower surface of the gate. The second step is arranged next to the first step and has an upper surface raised above the upper surface of the first step. The raised source/drain is configured to reduce resistance with a minimal increase of gate capacitance. The raised source/drain may be fabricated in one deposition step.

摘要翻译： 提供了一种用于提高半导体器件性能的结构，装置和方法。 半导体结构包括在平面源极/漏极上方的升高的源极/漏极区域。 升高的源极/漏极具有至少第一步骤和第二步骤，其间具有各种转变。 第一步是配置成优化半导体器件的性能并设置在门旁边的规定高度。 第一步在门的下表面上方具有顶表面。 第二步骤布置在第一步骤的旁边，并且具有在第一步骤的上表面上方升高的上表面。 升高的源极/漏极被配置为以最小的栅极电容增加来降低电阻。 升高的源极/漏极可以在一个沉积步骤中制造。