Array substrate, display panel and display device

    公开(公告)号:US11955075B2

    公开(公告)日:2024-04-09

    申请号:US17615514

    申请日:2021-01-15

    CPC classification number: G09G3/3233 H10K59/131 G09G2300/0426 G09G2320/0233

    Abstract: An array substrate has a display area and a non-display area including a first bonding region. The array substrate includes: a plurality of pixel columns disposed in the display area, each of the plurality of pixel columns including a plurality of light-emitting units that are arranged in a second direction, the second direction being perpendicular to a direction in which an edge of the display area proximate to the first bonding region extends; and at least three first power supply input terminals disposed in the first bonding region, each first power supply input terminal being connected to at least one pixel column of the plurality of pixel columns, so as to provide a first power supply signal to the at least one pixel column.

    Shift register unit and driving method thereof, gate driving circuit and display device

    公开(公告)号:US11568777B2

    公开(公告)日:2023-01-31

    申请号:US17327056

    申请日:2021-05-21

    Abstract: The present disclosure provides a shift register unit and a driving method thereof, a gate driving circuit and a driving method thereof, and a display device. The shift register unit includes: a first shift register, a second shift register and a switch control circuit, signal input terminals of the first and second shift registers are coupled to a cascade signal input terminal through the switch control circuit, the switch control circuit is configured to allow a current between the signal input terminal of the first shift register and the cascade signal input terminal or not, and allow a current between the signal input terminal of the second shift register and the cascade signal input terminal or not; the first shift register and the second shift register are configured such that at least one of them operates upon receiving a cascade signal provided by the cascade signal input terminal.

    Gate driving unit, gate driving method, gate driving circuitry and display device

    公开(公告)号:US11328642B2

    公开(公告)日:2022-05-10

    申请号:US17044148

    申请日:2020-03-18

    Abstract: The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuitry and a display device. The gate driving unit includes a reverse-phase gate driving signal output end, a normal-phase gate driving signal output end, an input circuitry, an output control circuitry, an input node control circuitry and an output circuitry. The input circuitry is configured to control an input end to be electrically connected to an input node under the control of a first clock signal. The output control circuitry is configured to control a potential at an output node under the control of a potential at the input node and a second clock signal. The input node control circuitry is configured to control the potential at the input node in accordance with the potential at the output node under the control of the second clock signal. The output circuitry is configured to output a reverse-phase gate driving signal and output a normal-phase gate driving signal in accordance with the potential at the output node.

    Driving circuit of display panel, driving method thereof, and display panel

    公开(公告)号:US11211027B2

    公开(公告)日:2021-12-28

    申请号:US16084027

    申请日:2018-04-08

    Abstract: The present disclosure is related to a driving circuit of a display panel. The driving circuit may include a turn-on voltage adjusting circuit. The turn-on voltage adjusting circuit may include a control subcircuit and a switching and voltage division subcircuit. The switching and voltage division subcircuit may include a switching subcircuit and a basic voltage division subcircuit. The switching subcircuit may be configured to perform voltage division of a signal outputted by the output terminal of the control subcircuit to form a voltage division feedback signal of the corresponding resolution under control of the control signal and output the voltage division feedback signal to the voltage division feedback node.

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