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公开(公告)号：US10140911B2
公开(公告)日：2018-11-27
申请号：US15508608
申请日：2016-09-22
发明人： Xiaoxiang Zhang , Zheng Liu , Mingxuan Liu , Huibin Guo , Xi Chen
摘要： The present application discloses a shift register unit for outputting a gate driving signal to control image display in an operation cycle including sequentially an input phase, an output phase, an output-suspending phase, the shift register unit including a first node-control circuit connected to a pull-up node and a first pull-down node; a second node-control circuit connected to a pull-down control node and the pull-up node; a pull-up circuit connected to the pull-up node, a first input terminal for receiving a first clock signal, and an output terminal for outputting the gate driving signal, and configured to control the first clock signal to be passed from the first input terminal to the output terminal when the pull-up node is at a first potential level; a third node-control circuit connected to the pull-up node, the first pull-down node, the pull-down control node, and a second input terminal for receiving a second clock signal; and configured to control the first pull-down node to receive the second clock signal from the second input terminal when the pull-down control node is at the first potential level; a first pull-down circuit connected to the first pull-down node and the output terminal to control a second potential level to be passed to the output terminal when the first pull-down node is at the first potential level; a fourth node-control circuit connected to a second pull-down node and the pull-down control node to control the second pull-down node at the second potential level during the input phase and the output phase and to maintain an inverted potential level between the second pull-down node and the first pull-down node during the output-suspending phase; and a second pull-down circuit connected to the second pull-down node and the output terminal to yield a second potential level at the output terminal when the second pull-down node is at the first potential level, the first node-control circuit being further connected to the second pull-down node to control the pull-up node at the second potential level when the second pull-down node is at the first potential level.
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公开(公告)号：US10042222B2
公开(公告)日：2018-08-07
申请号：US14744110
申请日：2015-06-19
发明人： Dongliang Wang , Xi Chen , Zhenyu Zhang , Linlin Wang , Bin Feng
IPC分类号： G01R31/26 , G02F1/1362 , H01L27/12
摘要： The present invention discloses a test device, a method of manufacturing the test device, and a display apparatus. The test device comprises a first test electrode and a second test electrode. The first test electrode is configured to electrically connect with an electrode layer of an array substrate, and the electrode layer is a gate electrode layer or a source-drain electrode layer. The second test electrode is configured to electrically connect with a first transparent conductive layer provided on the array substrate, and the first transparent conductive layer is electrically connected to a second transparent conductive layer provided on a color film substrate. Thereby, it is possible to test liquid crystal characteristics of the whole liquid crystal display panel by applying a DC voltage through the first test electrode and the second test electrode. Thereby, the test of the whole liquid crystal display panel may be directly finished under factory conditions without using the small liquid crystal test box or the like self-made in a laboratory. In this way, the testing result becomes more accurate, the testing process becomes more rapid, and the testing cost becomes lower.
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公开(公告)号：US09638972B2
公开(公告)日：2017-05-02
申请号：US14354186
申请日：2013-12-03
发明人： Xi Chen , Yuchun Feng , Jianfeng Yuan , Linlin Wang
IPC分类号： G02F1/1362 , G02F1/1368 , H01L27/12
CPC分类号： G02F1/136259 , G02F1/136286 , G02F1/1368 , G02F2001/136263 , H01L27/124 , H01L27/1244
摘要： An array substrate, a manufacturing method thereof and a display panel are disclosed. The array substrate includes: a base substrate, gate scanning lines, a gate-insulating layer, an active layer, data lines, a passivation layer, and pixel electrodes; the array substrate further includes: a bridge structure and a connection line corresponding to each data line; the bridge structure is located on the passivation layer and is provided in a same layer as the pixel electrodes; each connection line is located on the base substrate and is connected with the data line, through the bridge structure in an LED region and in a region under a scribe line of a counter substrate. Therefore the problem of defective display caused by breakage of data lines can be solved, and the display effect of a liquid crystal display device can be improved.
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4.发明申请公开(公告)号：US20160223901A1
公开(公告)日：2016-08-04
申请号：US14744392
申请日：2015-06-19
发明人： Xiaoxiang Zhang , Zheng Liu , Zongjie Guo , Zhichao Zhang , Mingxuan Liu , Xi Chen
CPC分类号： G02F1/1339 , G02F1/1341 , G02F2001/133354 , G03F1/42 , G03F1/54
摘要： An UV curing mask plate, comprising: a mask layer, wherein: the mask layer is arranged on the substrate, and has a position corresponding to alignment marks, selection marks and an area not covered by the sealing frame glue to be cured; the material of the mask layer is a material with the function of blocking UV light.
摘要翻译： 一种UV固化掩模板，包括：掩模层，其中：所述掩模层布置在所述基板上，并且具有对应于对准标记，选择标记和未被待固化的密封框胶水覆盖的区域的位置; 掩模层的材料是具有阻挡UV光的功能的材料。
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公开(公告)号：US20150318304A1
公开(公告)日：2015-11-05
申请号：US14314433
申请日：2014-06-25
发明人： Xiaowei Liu , Xi Chen , Zhenfei Cai , Yao Liu , Liangliang Li , Zongjie Guo
IPC分类号： H01L27/12 , H01L21/768
CPC分类号： G02F1/13458 , G02F2001/13456 , H01L21/768 , H01L27/124 , H01L27/1248 , H01L27/1259
摘要： The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.
摘要翻译： 本发明涉及阵列基板，其制造方法和显示装置。 阵列基板包括栅极线PAD区域和数据线PAD区域。 在阵列基板的栅极线PAD区域中，与栅极线平行且与栅极线电绝缘的栅极线配线设置在相邻的栅极线之间。 在阵列基板的数据线PAD区域中，在相邻数据线之间设置与数据线并行并与数据线电绝缘的数据线布线。 栅线布线和数据线布线都是导电布线段。 通过在PAD区域中形成栅极布线和数据线布线，可以在不降低产品显示性能的同时，提高产品耐刮擦能力。
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公开(公告)号：US11244642B2
公开(公告)日：2022-02-08
申请号：US16658385
申请日：2019-10-21
发明人： Bo Feng , Shijun Wang , Hongming Zhan , Xi Chen
IPC分类号： G09G3/36
摘要： Disclosed are a display panel, a display device, and a method for driving the same. The display panel includes a plurality of data lines extending in a first direction, and at least one signal compensation line extending in a second direction, insulated from and intersecting with the plurality of data lines, a compensation capacitor is arranged at a position where the plurality of data lines intersect with the signal compensation line, and one terminal of the compensation capacitor is connected with one of the plurality of data lines, and the other terminal of the compensation capacitor is connected with the signal compensation line.
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公开(公告)号：US10916213B2
公开(公告)日：2021-02-09
申请号：US16470835
申请日：2018-07-12
发明人： Bo Feng , Shijun Wang , Xi Chen , Hongming Zhan
摘要： A shift register includes first, second and third output sub-circuits, first and second pull-down sub-circuits, and a selection sub-circuit. The first output sub-circuit is coupled to a pull-up node, a first output terminal, and a first clock signal terminal. The second output sub-circuit is coupled to the first clock signal terminal, the selection sub-circuit, and a second output terminal. The third output sub-circuit is coupled to a second clock signal terminal, the selection sub-circuit, and the second output terminal. The selection sub-circuit is coupled to the second and third output sub-circuits, the pull-up node, and a gating signal terminal. The first pull-down sub-circuit is coupled to a first pull-down node, the first output terminal, a second voltage terminal, and the pull-up node. The second pull-down sub-circuit is coupled to the second output terminal, a first voltage terminal, and the first pull-down node.
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公开(公告)号：US10510279B2
公开(公告)日：2019-12-17
申请号：US15751120
申请日：2017-07-24
发明人： Xiaoxiang Zhang , Xi Chen , Mingxuan Liu , Huibin Guo , Liping Luo
摘要： The present disclosure provides a shift register unit, a gate scanning circuit, a driving method, and a display apparatus. The shift register unit comprises a reset circuit configured to transmit a signal from a signal control terminal to a first node and a shift register unit signal output terminal under the control of a reset control signal input terminal; a first pull-down control circuit configured to transmit the signal from the signal control terminal to the first node and the shift register unit signal output terminal under the control of a second node; and a second pull-down control circuit configured to transmit the signal from the signal control terminal to the first node and the shift register unit signal output terminal under the control of a third node control signal input terminal coupled to a third node, so as to cooperate with the reset circuit and the first pull-down control circuit to jointly reset the shift register unit in a phase in which output of the shift register unit should not occur, thereby effectively preventing output of the shift register unit from occurring in the phase in which output of the shift register unit should not occur.
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公开(公告)号：US10371997B2
公开(公告)日：2019-08-06
申请号：US15726995
申请日：2017-10-06
发明人： Xiaowei Liu , Xi Chen , Zhenfei Cai , Yao Liu , Liangliang Li , Zongjie Guo
IPC分类号： G02F1/1345 , H01L27/12 , H01L21/768
摘要： The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.
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公开(公告)号：US09721979B1
公开(公告)日：2017-08-01
申请号：US15106052
申请日：2016-01-14
发明人： Zheng Liu , Tsung Chieh Kuo , Xi Chen , Xiaoxiang Zhang , Zhichao Zhang , Mingxuan Liu
IPC分类号： H01L21/00 , H01L21/84 , G02F1/1343 , H01L27/12 , H01L29/66 , G02F1/1368 , G02F1/1333
CPC分类号： H01L27/1288 , G02F1/133345 , G02F1/134309 , G02F1/13439 , G02F1/136227 , G02F1/1368 , G02F2001/134318 , G02F2001/134372 , G02F2201/121 , G02F2201/123 , H01L21/77 , H01L27/12 , H01L29/66765
摘要： A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.
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