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公开(公告)号：US20160299392A1
公开(公告)日：2016-10-13
申请号：US14771748
申请日：2015-04-20
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hongfei CHENG , Jianbo XIAN , Yong QIAO , Yongchun LU , Jian XU , Yongda MA , Wenbo LI , Pan LI
IPC: G02F1/1343 , G02F1/1362 , G02F1/1368
CPC classification number: G02F1/134336 , G02F1/133707 , G02F1/134309 , G02F1/1362 , G02F1/136213 , G02F1/13624 , G02F1/136286 , G02F1/1368 , G02F2001/134318 , G02F2001/134345 , G02F2201/121 , G02F2201/123
Abstract: A display substrate includes a first base substrate; a gate line, a data line and a common electrode line arranged on the first base substrate; a plurality of pixel units each including a first sub-pixel electrode, a second sub-pixel electrode, a first thin film transistor, a second thin film transistor and a third thin film transistor; and a charge adjustment-control line arranged on the first base substrate, where the charge adjustment-control line and the gate line are between the first sub-pixel electrode and the second sub-pixel electrode. The first thin film transistor is connected to the gate line, the data line and the first sub-pixel electrode; the second thin film transistor is connected to the gate line, the data line and the second sub-pixel electrode; the third thin film transistor is connected to the charge adjustment control line, the first sub-pixel electrode and the common electrode line.
Abstract translation: 显示基板包括：第一基底; 布线在第一基底上的栅极线，数据线和公共电极线; 多个像素单元，每个像素单元包括第一子像素电极，第二子像素电极，第一薄膜晶体管，第二薄膜晶体管和第三薄膜晶体管; 以及电荷调节控制线，其布置在所述第一基底上，所述电荷调节控制线和所述栅极线在所述第一子像素电极和所述第二子像素电极之间。 第一薄膜晶体管连接到栅极线，数据线和第一子像素电极; 第二薄膜晶体管连接到栅极线，数据线和第二子像素电极; 第三薄膜晶体管连接到电荷调节控制线，第一子像素电极和公共电极线。
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62.发明申请公开(公告)号：US20160252793A1
公开(公告)日：2016-09-01
申请号：US14769405
申请日：2014-11-27
Applicant: BOE Technology Group Co., Ltd.
Inventor： Hongfei CHENG , Yong QIAO , Jianbo XIAN , Wenbo LI , Pan LI
IPC: G02F1/1362 , H01L29/786 , G02F1/1333 , G02F1/1368 , G02F1/1343 , H01L27/12 , H01L29/66
CPC classification number: H01L27/124 , G02F1/133345 , G02F1/1343 , G02F1/134309 , G02F1/134363 , G02F1/13439 , G02F1/1362 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/134318 , G02F2001/134345 , G02F2001/134372 , G02F2001/136218 , G02F2001/136295 , G02F2201/121 , H01L27/1222 , H01L27/1225 , H01L27/1248 , H01L27/1259 , H01L29/66765 , H01L29/66969 , H01L29/78633 , H01L29/78669 , H01L29/7869
Abstract: The present disclosure provides an array substrate, a display panel, a display device and a method for manufacturing the array substrate. The array substrate includes: a plurality of gate lines and a plurality of data lines arranged in a crisscross manner on a base substrate, so as to define a plurality of subpixels; and a common electrode arranged opposite to each of the plurality of subpixels;. At least one of the subpixels is provided with a common electrode line connected to the common electrode at an identical subpixel region.
Abstract translation: 本发明提供一种阵列基板，显示面板，显示装置以及阵列基板的制造方法。 阵列基板包括：多个栅极线和在基底基板上以十字交叉的方式布置的多条数据线，以便限定多个子像素; 以及与所述多个子像素中的每一个相对配置的公共电极。 子像素中的至少一个在相同的子像素区域设置有与公共电极连接的公共电极线。
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公开(公告)号：US20240276848A1
公开(公告)日：2024-08-15
申请号：US18022171
申请日：2022-05-25
Inventor： Xueguang HAO , Yong QIAO , Xinyin WU , Xinguo LI
CPC classification number: H10K59/879 , H10K59/351 , H10K59/352 , H10K59/353 , H10K59/38 , H10K59/8792
Abstract: A display substrate, a preparing method therefor, and a display apparatus are disclosed. The display substrate includes a first display region (100) and a second display region (200), the second display region (200) at least partially surrounds the first display region (100), the first display region (100) is configured to perform image display and make light pass through, and the second display region (200) is configured to perform image display; in a plane perpendicular to the display substrate, the first display region (100) at least includes a display structure layer disposed on the base substrate (10) and a light-processing layer (50) disposed on a side of the display structure layer away from the base substrate (10), and the light-processing layer (50) at least includes a light-taking structure for improving light output efficiency.
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公开(公告)号：US20220334425A1
公开(公告)日：2022-10-20
申请号：US17855390
申请日：2022-06-30
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hui LI , Xinyin WU , Yong QIAO , Jianbo XIAN
IPC: G02F1/1339 , G02F1/1362 , G02F1/1335
Abstract: A liquid crystal display panel includes an array substrate and an opposite substrate that are disposed opposite to each other; the liquid crystal display panel has a display region and at least one non-display region disposed beside the display region. The array substrate is of a multi-layer structure and includes a pixel electrode layer and a plurality of protrusions disposed in the at least one non-display region, and the opposite substrate includes a common electrode layer. A protrusion has a structure including at least one film, and a film of the at least one film is located in a layer included in the array substrate.
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65.发明申请公开(公告)号：US20220319391A1
公开(公告)日：2022-10-06
申请号：US17807908
申请日：2022-06-21
Inventor： Jianbo XIAN , Chen XU , Xueguang HAO , Yong QIAO
IPC: G09G3/20
Abstract: A shift register unit, a circuit structure, a gate drive circuit, a drive circuit and a display device are provided. A shift register unit includes a substrate and an input circuit, a reset circuit, a first output circuit, a first output terminal, a first connection conductive portion connecting both the input circuit and the reset circuit, a second connection conductive portion connecting both the reset circuit and the first output circuit, and a third connection conductive portion connecting both the first output circuit and the first output terminal, all of which are on the substrate.
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Patent Agency Ranking
公开(公告)号：US20220276539A1
公开(公告)日：2022-09-01
申请号：US17747278
申请日：2022-05-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chunping LONG , Yong QIAO , Xinyin WU
IPC: G02F1/1337 , G02F1/1343
Abstract: A method for manufacturing an array substrate includes: providing a base substrate; forming gate lines and data lines intercrossing each other, the gate lines and the data lines define multiple pixel units. Multiple pixel regions are formed in each pixel unit, a display electrode having a slit is formed in each pixel region. Each data line includes multiple data line segments. In each pixel unit, each of a part of the pixel regions has a display electrode whose slit is parallel to a data line segment adjacent to this pixel region; each of another part of the pixel regions has a display electrode whose slit is non-parallel to a data line segment adjacent to this pixel region. The display electrodes in each of the pixel units are located at a same side of the gate line to which the pixel unit where the display electrodes are located is coupled.
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公开(公告)号：US20220238564A1
公开(公告)日：2022-07-28
申请号：US17658636
申请日：2022-04-08
IPC: H01L27/12 , G02F1/1362 , H01L27/02
Abstract: The present disclosure provides a display substrate and a display device. A display substrate provided by an embodiment of the present disclosure includes: a display region and a peripheral region surrounding the display region; the display region includes: a plurality of gate lines, a plurality of data lines, and a plurality of pixel units, and each of the plurality of pixel units includes a driving transistor and a pixel electrode that are connected to each other; the peripheral region includes: signal lines and at least one electrostatic discharge structure for performing electrostatic discharge on the signal lines, and the electrostatic discharge structure includes a comb-shaped sixth electrostatic discharge pattern and a seventh electrostatic discharge pattern.
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公开(公告)号：US20210407402A1
公开(公告)日：2021-12-30
申请号：US16477308
申请日：2019-01-10
Inventor： Chen XU , Xueguang HAO , Yong QIAO , Xinyin WU
IPC: G09G3/3233
Abstract: A display panel and a display device. The display panel includes a pixel circuit structure, a data line and a voltage signal line. The data line is connected to the pixel circuit structure to provide a data signal; the voltage signal line is connected to the pixel circuit structure to provide a voltage signal, the voltage signal is a constant voltage signal; the pixel circuit structure includes a first stabilization capacitor provided between the data line and the voltage signal line.
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69.发明申请公开(公告)号：US20210373374A1
公开(公告)日：2021-12-02
申请号：US16959003
申请日：2019-12-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Hui LI , Xinyin WU , Yong QIAO , Jianbo XIAN
IPC: G02F1/1339 , G02F1/1362 , G02F1/1335
Abstract: A liquid crystal display panel includes a first substrate and a second substrate that are disposed opposite to each other; the liquid crystal display panel has a display region and at least one non-display region disposed beside the display region. One of the first substrate and the second substrate includes a plurality of protrusions disposed in the at least one non-display region, and the other of the first substrate and the second substrate includes a plurality of grooves disposed in the at least one non-display region, each protrusion of the plurality of protrusions is corresponding to one groove of the plurality of grooves, and the protrusion is matched with the corresponding groove.
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公开(公告)号：US20210358407A1
公开(公告)日：2021-11-18
申请号：US16480493
申请日：2019-01-11
Inventor： Chen XU , Xueguang HAO , Jianbo XIAN , Yong QIAO , Xinyin WU
IPC: G09G3/3233 , H01L27/32
Abstract: A display panel and a display device are provided. The display panel includes: a substrate, a plurality of pixel units, a functional signal line, and a first conductive structure. The substrate includes a display area and a peripheral area on at least one side of the display area, the plurality of pixel units are in the display area, each pixel unit includes a light-emitting unit and a pixel circuit structure for providing a driving current to the light-emitting unit, and the light-emitting unit is an electroluminescent element. The functional signal line is connected with the pixel circuit structure of each pixel unit and provides a common voltage signal for the pixel circuit structure. The first conductive structure is connected in parallel with the functional signal line and is located at a layer different from that of the functional signal line.
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