公开(公告)号：US5840451A

公开(公告)日：1998-11-24

申请号：US760029

申请日：1996-12-04

申请人： Bradley T. Moore ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Derick J. Wristers

发明人： Bradley T. Moore ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Mark W. Michael ,  Derick J. Wristers

IPC分类号： G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70391 ,  G03F7/20 ,  Y10S430/146 ,  Y10S430/168

摘要： A photolithographic system includes individually controllable radiation sources for forming an image pattern on an image plane without using a reticle or mask during fabrication of an integrated circuit device. The radiation sources are selectively activated as they scan the image plane. The image pattern can consist of parallel lines having identical widths and varying lengths, or alternatively, pixels having identical shapes and sizes. The radiation sources can be arranged as a linear array, or a staggered array, to achieve the desired linear density. Suitable radiation sources include light pipes, light emitting diodes, and laser diodes. Preferably, each of the activated radiation sources provides an exposure field of less than 0.1 microns on the image plane, and at least two of the radiation sources must be activated to provide the minimum line width of the image pattern.

摘要翻译： 光刻系统包括单独可控的辐射源，用于在集成电路器件的制造期间在图像平面上形成图像图案而不使用掩模版或掩模。 当扫描图像平面时，辐射源被选择性地激活。 图像图案可以由具有相同宽度和变化长度的平行线组成，或者替代地，具有相同形状和尺寸的像素。 辐射源可以被布置为线性阵列或交错阵列，以实现期望的线密度。 合适的辐射源包括光管，发光二极管和激光二极管。 优选地，每个激活的辐射源在图像平面上提供小于0.1微米的曝光场，并且必须激活至少两个辐射源以提供图像图案的最小线宽。

公开(公告)号：US5801075A

公开(公告)日：1998-09-01

申请号：US739593

申请日：1996-10-30

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8238

CPC分类号： H01L29/41775 ,  H01L29/66621 ,  H01L29/78

摘要： An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.

摘要翻译： 公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽，与侧壁和底表面相邻的金属间隔物，位于金属间隔物之间​​的底表面上的栅极绝缘体，金属间隔物上的保护绝缘体，栅电极 在栅极绝缘体和保护绝缘体上，以及与底表面相邻的源极和漏极。 形成IGFET的方法包括将掺杂层注入到衬底中，完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域，施加高温退火以扩散 在底表面下方的源极和漏极区域，在衬底上沉积导电金属的覆盖层，并施加各向异性蚀刻以形成金属间隔物，在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体， 覆盖衬底上的栅电极材料层，并且对栅电极材料进行抛光，使得栅电极基本上与衬底的顶表面对准。 有利地，沟道长度显着小于沟槽长度，并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。

公开(公告)号：US06188114B1

公开(公告)日：2001-02-13

申请号：US09204016

申请日：1998-12-01

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L31119

CPC分类号： H01L29/41783 ,  H01L29/41775 ,  H01L29/66575 ,  H01L29/6659

摘要： An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

摘要翻译： 公开了具有金属间隔物的IGFET。 IGFET在半导体衬底上的栅极绝缘体上包括栅电极。 侧壁绝缘体与栅电极的相对的垂直边缘相邻，并且金属间隔件形成在衬底上并且与侧壁绝缘体相邻。 金属间隔物与栅电极电绝缘，但是漏极和源极的接触部分。 优选地，金属间隔件邻近侧壁绝缘体之下的栅极绝缘体的边缘。 通过在衬底上沉积金属层然后施加各向异性蚀刻来形成金属间隔物。 在一个实施例中，金属间隔物接触轻掺杂和重掺杂的漏极和源极区域，从而增加重掺杂漏极和源极区域之间的导电性以及栅电极下面的沟道。 金属间隔物还可以提供低电阻漏极和源极触点。

公开(公告)号：US6166354A

公开(公告)日：2000-12-26

申请号：US876381

申请日：1997-06-16

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： C30B31/12 ,  C30B31/18 ,  F27B5/14

CPC分类号： C30B31/18 ,  C30B31/12

摘要： An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.

摘要翻译： 在退火步骤期间执行半导体器件的电特性的光学监测，以检测时间退火完成并发生激活。 在退火期间进行表面光电压测量以监测衬底晶片的表面上的电荷状态，以确定衬底何时完全退火。 监测表面光电压测量，检测退火时间，并控制所选择的过退火。 执行表面光电压（SPV）测量以确定在硅晶格中退火掺杂剂或杂质如硼或磷的点。 在一些实施例中，将检测点用作RTA退火系统中的反馈信号，以调整用于退火和激活均匀性控制的退火灯组。 检测点也用于终止退火过程以最小化Dt。

公开(公告)号：US6146978A

公开(公告)日：2000-11-14

申请号：US73639

申请日：1998-05-06

申请人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark W. Michael ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Mark I. Gardner ,  Frederick N. Hause ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L21/44 ,  H01L21/4763 ,  H01L31/119

CPC分类号： H01L21/823871 ,  H01L21/76802 ,  H01L21/76895

摘要： An interlevel interconnect is formed in a window opened through an isolation layer and through an etch barrier to expose an electrode surface and an adjacent isolation barrier. The interlevel interconnect may be disposed on substantially all of a portion of the underlying electrode such as an insulated gate field effect transistor (IGFET) source/drain region surface. The etch barrier provides controlled etching to allow for overlap of the interlevel interconnect onto the isolation barrier without increased parasitic capacitance relative to conventional contact misalignments. Furthermore, allaying concerns of overlapping allows for increased utilization of source/drain region surface area by the interlevel interconnect. Furthermore, the etch barrier allows the interlevel interconnect to strap electrodes of a plurality of circuit devices while exhibiting nominal if any substrate to interlevel interconnect leakage currents.

摘要翻译： 在通过隔离层打开的窗口中并通过蚀刻屏障形成层间互连，以露出电极表面和相邻隔离屏障。 层间互连可以布置在底层电极的基本上全部的一部分上，例如绝缘栅场效应晶体管（IGFET）源/漏区表面。 蚀刻屏障提供受控的蚀刻，以允许层间互连重叠在隔离屏障上，而不增加寄生电容，相对于传统的接触不对准。 此外，消除重叠的关注允许通过层间互连增加源/漏区表面积的利用。 此外，蚀刻屏障允许层间互连以多个电路器件的带状电极同时显示标称的任何衬底以互连互连漏电流。

公开(公告)号：US6096639A

公开(公告)日：2000-08-01

申请号：US056835

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76895

摘要： A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.

摘要翻译： 通过在半导体结构的选定区域中形成硅化物层然后沉积覆盖在半导体结构上的基本均匀的过渡或难熔金属层来形成局部互连（LI）结构。 在硅化物和金属层之间的中间绝缘层中沉积金属局部互连以限定接触开口或通孔。 在一些实施例中，钛是用于形成局部互连的合适金属。 用于硅化物层形成的合适的选定区域包括例如硅化源极/漏极（S / D）区域和硅化物栅极接触区域。 硅化区域形成均匀的结构，用于电耦合到作为一个或多个半导体器件的部分的下掺杂区域。 在需要蚀刻阻挡层用于图案化金属膜的集成电路中，在沉积金属膜之前沉积第一可选绝缘层。 在一个示例中，绝缘层是通常小于10nm厚度的二氧化硅（氧化物）层。

公开(公告)号：US6087706A

公开(公告)日：2000-07-11

申请号：US56834

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/265 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/78 ,  H01L29/00 ,  H01L29/94

CPC分类号： H01L21/26586 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/41766 ,  H01L29/66636 ,  H01L29/7833

摘要： A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are self-aligned to both the gate electrode and the trench side-walls. A dielectric spacer is formed adjacent the gate electrode and extending to the trench side-walls. In this manner, the spacers essentially cover the LDD regions. Source and drain regions are formed that are adjacent the trench side-walls wherein the spacer serves to protect at least a portion of the LDD regions to maintain a spacing of the S/D regions from the gate electrode edge. In this manner an advantageously lowered E.sub.M provided by LDD regions is maintained. In some embodiments of the present invention, S/D regions are formed by implantation through the trench side-walls.

摘要翻译： 描述了一种形成在由浅沟槽隔离区域的侧壁限定的有源区域内的晶体管的半导体集成电路及其制造方法。 在有源区域的一部分上形成栅电极，形成与栅极电极和沟槽侧壁自对准的LDD区域。 形成在栅电极附近并延伸到沟槽侧壁的电介质垫片。 以这种方式，间隔件基本上覆盖LDD区域。 形成与沟槽侧壁相邻的源极区和漏极区，其中间隔物用于保护LDD区的至少一部分以保持S / D区与栅电极边缘的间隔。 以这种方式，维持由LDD区域提供的有利的降低的EM。 在本发明的一些实施例中，通过在沟槽侧壁上注入形成S / D区域。

公开(公告)号：US06661057B1

公开(公告)日：2003-12-09

申请号：US09056836

申请日：1998-04-07

申请人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Robert Dawson ,  Mark I. Gardner ,  Frederick N. Hause ,  H. Jim Fulford, Jr. ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L27088

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76855 ,  H01L29/66484 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7831 ,  H01L29/7833 ,  Y10S257/90

摘要： A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.

摘要翻译： 晶体管形成在具有分段栅极结构的有源区中。 分段栅结构有利地提供了在晶体管内形成的沟道区的动态控制。 轻掺杂的源极和漏极（LDD）区域形成为与栅电极对准。 在与栅电极的暴露表面相邻形成绝缘层之后，形成布置在LDD区域上方的导电间隔物。 这些间隔物通过绝缘层与栅电极电隔离。 形成重掺杂的源极和漏极（S / D）区域，其与间隔物对准，并且例如通过提供给导电间隔物，栅电极和S / D区域的自对准硅化物工艺进行电接触。 所描述的结构有利地通过对S / D区域的LDD部分的动态独立控制来提供通道区域的动态控制。

公开(公告)号：US06410409B1

公开(公告)日：2002-06-25

申请号：US08741799

申请日：1996-10-31

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21265

CPC分类号： H01L21/8238 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/74

摘要： Boron forming a deep P+ layer within a semiconductor substrate upwardly diffuses during subsequent heat treatment operations such as annealing. A method for retarding this upward diffusion of boron includes implanting nitrogen to form a nitrogen barrier layer near the upper boundary of the P+ layer and well below transistor source/drain regions. One embodiment includes a lightly doped epitaxial layer formed upon an underlying P+ substrate. In another embodiment, a deep boron implant forms a P+ layer within a P− substrate, and affords many of the advantages of an epitaxial layer without actually requiring such an epitaxial layer. The nitrogen implant is performed at a preferred energy of 1-3 MeV to form the implanted nitrogen barrier layer at a depth in the range of 1-5 microns. Oxygen may also be implanted to form a diffusion barrier layer to retard the upward diffusion of arsenic or phosphorus forming a deep N+ layer.

摘要翻译： 在随后的热处理操作（例如退火）期间，在半导体衬底内形成深P +层的硼向上扩散。 用于延迟硼的这种向上扩散的方法包括注入氮以在P +层的上边界附近形成氮阻挡层，并且远低于晶体管源/漏区。 一个实施例包括形成在下面的P +衬底上的轻掺杂的外延层。 在另一个实施例中，深硼注入在P-衬底内形成P +层，并提供外延层的许多优点，而不需要这样的外延层。 以1-3MeV的优选能量进行氮注入，以在1-5微米范围内的深度形成注入的氮阻挡层。 氧也可以被植入以形成扩散阻挡层，以阻止形成深N +层的砷或磷的向上扩散。

公开(公告)号：US06380055B2

公开(公告)日：2002-04-30

申请号：US09177043

申请日：1998-10-22

申请人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Frederick N. Hause ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L213205

CPC分类号： H01L29/4925 ,  H01L21/28035 ,  H01L21/32155

摘要： A diffusion-retarding barrier region is incorporated into the gate electrode to reduce the downward diffusion of dopant toward the gate dielectric. The barrier region is a nitrogen-containing diffusion retarding barrier region formed between two separately formed layers of polysilicon. The upper layer of polysilicon is doped more heavily than the lower layer of polysilicon, and the barrier region serves to keep most of the dopant within the upper layer of polysilicon, and yet may allow some of the dopant to diffuse into the lower layer of polysilicon. The barrier region may be formed, for example, by annealing the first polysilicon layer in an nitrogen-containing ambient to form a nitrided layer at the top surface of the first polysilicon layer. The barrier region may alternatively be formed by depositing a nitrogen-containing layer, such as a silicon nitride or titanium nitride layer, on the top surface of the first polysilicon layer. The thickness of the nitrogen-containing layer is preferably approximately 5-15 Å thick. Any nitrogen residing at the top of the gate dielectric may be kept to a concentration less than approximately 2%. The present invention is particularly well suited to thin gate dielectrics, such as a those having a thickness of approximately 25-60 Å, when using a p-type dopant, such as boron.

摘要翻译： 扩散阻滞屏障区域被结合到栅电极中以减少掺杂剂朝向栅极电介质的向下扩散。 阻挡区域是在两个单独形成的多晶硅层之间形成的含氮扩散阻滞区域。 多晶硅的上层比多晶硅的下层掺杂更多，并且势垒区域用于将大部分掺杂剂保持在多晶硅的上层内，并且还可以允许一些掺杂剂扩散到多晶硅的下层 。 阻挡区域可以例如通过在含氮环境中退火第一多晶硅层以在第一多晶硅层的顶表面处形成氮化层而形成。 可以通过在第一多晶硅层的顶表面上沉积含氮层，例如氮化硅或氮化钛层来形成阻挡区。 含氮层的厚度优选为约5〜约厚。 驻留在栅极电介质顶部的任何氮可以保持在小于约2％的浓度。 当使用诸如硼的p型掺杂剂时，本发明特别适用于薄栅极电介质，例如厚度大约为25埃的那些。