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61.发明授权I/O address translation method for specifying a relaxed ordering for I/O accesses 失效用于指定I / O访问放松排序的I / O地址转换方法公开(公告)号：US07721023B2
公开(公告)日：2010-05-18
申请号：US11274842
申请日：2005-11-15
IPC分类号： G06F7/02
CPC分类号： G06F13/12 , G06F12/1081
摘要： An I/O address translation method for specifying relaxed ordering for I/O accesses are provided. With the apparatus and method, storage ordering (SO) bits are provided in an I/O address translation data structure, such as a page table or segment table. These SO bits define the order in which reads and/or writes initiated by an I/O device may be performed. These SO bits are combined with an ordering bit, e.g., the Relaxed Ordering Attribute bit of PCI Express, on the I/O interface. The weaker ordering indicated either in the I/O address translation data structure or in the I/O interface relaxed ordering bit is used to control the order in which I/O operations may be performed.
摘要翻译： 提供了一种用于指定I / O访问的轻松顺序的I / O地址转换方法。 利用该装置和方法，在I / O地址转换数据结构（例如页表或段表）中提供存储顺序（SO）位。 这些SO位定义可以执行由I / O设备启动的读取和/或写入的顺序。 这些SO位与I / O接口上的排序位（例如PCI Express的轻松排序属性位）组合。 在I / O地址转换数据结构或I / O接口松弛排序位中指示的较弱排序用于控制可能执行I / O操作的顺序。
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公开(公告)号：US20090217300A1
公开(公告)日：2009-08-27
申请号：US12361907
申请日：2009-01-29
CPC分类号： G06F13/24
摘要： A system and method for communicating with a processor event facility are provided. The system and method make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于与处理器事件设施进行通信的系统和方法。 系统和方法利用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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63.发明授权公开(公告)号：US07484052B2
公开(公告)日：2009-01-27
申请号：US11120909
申请日：2005-05-03
IPC分类号： G06F12/00
CPC分类号： G06F12/06
摘要： The present invention utilizes the good qualities of a single address concentrator (AC), without any extra chips or wires, and distributes the AC function among the various chips, making use of the fact that each chip in the system has a copy of the AC function therein. Using the distributed address concentrator function, each chip will handle approximately one-fourth of the command traffic and the average latency of servicing the commands will be approximately the same across each chip in the system.
摘要翻译： 本发明利用单个地址集中器（AC）的良好品质，而不需要任何额外的芯片或电线，并且在各种芯片之间分配AC功能，利用系统中的每个芯片具有AC的副本 功能。 使用分布式地址集中器功能，每个芯片将处理大约四分之一的命令流量，并且在系统中的每个芯片上的平均服务延迟将大致相同。
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64.发明申请Virtual world event notification from a persistent world game server in a logically partitioned game console 审中-公开虚拟世界事件通知从持久的世界游戏服务器在一个逻辑分区的游戏机公开(公告)号：US20080090659A1
公开(公告)日：2008-04-17
申请号：US11548904
申请日：2006-10-12
IPC分类号： A63F9/24
CPC分类号： A63F13/85 , A63F13/12 , A63F13/352 , A63F2300/537 , A63F2300/5533 , A63F2300/575
摘要： A mechanism is provided for generating event notifications for offline characters from within a persistent world online game. A player agent for an offline player runs in a secondary partition in a video game console while a primary application runs in a main partition. The offline player agent includes an event monitor that monitors for events that occur in a persistent virtual world maintained by a game server. When a game event occurs that triggers an offline player rule, the player agent composes an event notification message and presents the message to the offline player through speech or through an interface within the primary application. Event notification messages may include images, voice (text-to-speech), sound, or video.
摘要翻译： 提供了一种用于从永久性世界在线游戏内产生离线角色的事件通知的机制。 主要应用程序在主分区中运行时，用于离线播放器的播放器代理在视频游戏控制台的辅助分区中运行。 离线播放器代理包括事件监视器，其监视由游戏服务器维护的持久虚拟世界中发生的事件。 当触发离线播放器规则的游戏事件发生时，播放器代理构成事件通知消息，并通过语音或通过主应用程序中的界面将消息呈现给离线播放器。 事件通知消息可以包括图像，语音（文本到语音），声音或视频。
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公开(公告)号：US07349762B2
公开(公告)日：2008-03-25
申请号：US11271460
申请日：2005-11-10
IPC分类号： G06F17/40
CPC分类号： G05D23/19
摘要： Systems and methods for sensing temperatures of multiple functional blocks within a digital device and controlling the operation of these functional blocks in a manner that selectively reduces temperatures associated with some of the functional blocks, but not others. One embodiment comprises an integrated circuit having multiple functional blocks (such as processor cores) and a set of thermal sensors coupled to sense the temperatures of the functional blocks. The integrated circuit includes control circuitry configured to receive signals from the thermal sensors, detect thermal events in the functional blocks and to individually adjust operation of the functional blocks to reduce the temperatures causing the thermal events. In one embodiment, the control circuitry includes a detection/control circuit coupled to each of the functional blocks and a thermal management unit configured to evaluate detected thermal events and to determine actions to be taken in response to the thermal events.
摘要翻译： 用于感测数字设备内的多个功能块的温度的系统和方法，并且以选择性地降低与一些功能块相关联的温度而不是其它功能块的方式来控制这些功能块的操作。 一个实施例包括具有多个功能块（例如处理器核）的集成电路和耦合以感测功能块的温度的一组热传感器。 集成电路包括控制电路，其被配置为从热传感器接收信号，检测功能块中的热事件并且单独地调整功能块的操作以降低导致热事件的温度。 在一个实施例中，控制电路包括耦合到每个功能块的检测/控制电路和被配置为评估检测到的热事件并且确定响应于热事件而采取的动作的热管理单元。
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公开(公告)号：US20080071955A1
公开(公告)日：2008-03-20
申请号：US11532987
申请日：2006-09-19
申请人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
发明人： Charles R. Johns , David J. Krolak , Peichun P. Liu , Alvan W. Ng
IPC分类号： G06F13/36
CPC分类号： G06F11/362 , G06F11/0724 , G06F11/0757
摘要： A mechanism is provided for resolving livelock conditions in a multiple processor data processing system. When a bus unit detects a timeout condition, or potential timeout condition, the bus unit activates a livelock resolution request signal. A livelock resolution unit receives livelock resolution requests from the bus units and signals an attention to a control processor. The control processor performs actions to attempt to resolve the livelock condition. Once a bus unit that issued a livelock resolution request has managed to successfully issue its command, it deactivates its livelock resolution request. If all livelock resolution request signals are deactivated, then the control processor instructs the bus and all bus units to resume normal activity. On the other hand, if the control processor determines that a predetermined amount of time passes without any progress being made, it determines that a hang condition has occurred.
摘要翻译： 提供了用于解决多处理器数据处理系统中的活锁状态的机制。 当总线单元检测到超时条件或潜在的超时条件时，总线单元激活一个动态锁定解析请求信号。 活动锁定解析单元从总线单元接收实时锁定解析请求并且向控制处理器发出注意。 控制处理器执行动作以尝试解决动态锁定状态。 一旦发出了一个活动锁解决方案请求的总线单元成功地发出了它的命令，它将取消激活其活动锁定解决请求。 如果所有活动锁定解析请求信号被去激活，则控制处理器指令总线和所有总线单元恢复正常活动。 另一方面，如果控制处理器确定预定量的时间通过而没有进行任何进展，则确定已经发生了挂起状况。
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67.发明申请System and Method for Providing a Mediated External Exception Extension for a Microprocessor 审中-公开为微处理器提供介入的外部异常扩展的系统和方法公开(公告)号：US20080034193A1
公开(公告)日：2008-02-07
申请号：US11462601
申请日：2006-08-04
IPC分类号： G06F7/38
CPC分类号： G06F13/24 , G06F9/32 , G06F9/4812 , G06F2209/481
摘要： A system and method for providing a mediated external exception extension for a microprocessor are provided. With the system and method, in response to an external exception, a hypervisor determines if the associated external interrupt is directed to a logical partition (LPAR) that has external interrupt handling enabled. If so, the hypervisor sets appropriate state restore registers (SRRs) and passes control to an external interrupt handler of the LPAR. If external interrupt handling is not currently enabled by the LPAR, the hypervisor sets a mediated exception request and returns control to the LPAR. Once the operating system of the logical partition re-enables external interrupt handling, a mediated external interrupt occurs, state information for the LPAR is set in the SRRs, and the external interrupt handler of the LPAR is invoked. In this way, external interrupts may be received by the hypervisor even when external interrupt handling is disabled.
摘要翻译： 提供了一种用于为微处理器提供介导的外部异常扩展的系统和方法。 利用系统和方法，响应于外部异常，管理程序确定相关联的外部中断是否被引导到启用了外部中断处理的逻辑分区（LPAR）。 如果是这样，管理程序设置适当的状态恢复寄存器（SRR），并将控制权传递给LPAR的外部中断处理程序。 如果LPAR当前未启用外部中断处理，管理程序将设置介入的异常请求并将控制权返回给LPAR。 一旦逻辑分区的操作系统重新启用外部中断处理，就会发生中介的外部中断，LPAR的状态信息设置在SRR中，并且调用LPAR的外部中断处理程序。 以这种方式，即使禁用外部中断处理，管理程序也可以接收外部中断。
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公开(公告)号：US09696996B2
公开(公告)日：2017-07-04
申请号：US13434903
申请日：2012-03-30
CPC分类号： G06F9/30076 , G06F9/325 , G06F9/3834 , G06F9/3838
摘要： Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor, Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.
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公开(公告)号：US09696995B2
公开(公告)日：2017-07-04
申请号：US12649805
申请日：2009-12-30
CPC分类号： G06F9/30076 , G06F9/325 , G06F9/3834 , G06F9/3838
摘要： Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor. Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.
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公开(公告)号：US20120191953A1
公开(公告)日：2012-07-26
申请号：US13434903
申请日：2012-03-30
CPC分类号： G06F9/30076 , G06F9/325 , G06F9/3834 , G06F9/3838
摘要： Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor, Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.
摘要翻译： 提供了在运行时提取数据依赖关系的机制。 利用这些机制，执行具有循环的一部分代码。 为循环生成第一个并行执行组，该组包括循环的迭代次数小于循环迭代次数的总数。 通过并行执行每个迭代来执行第一个并行执行组。 用于迭代的存储数据存储在处理器的对应存储高速缓存中，处理器的依赖性检查逻辑针对每个迭代确定迭代是否具有数据依赖性。 只有确定了没有数据依赖关系的商店的商店数据被提交到内存。
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