公开(公告)号：US06262615B1

公开(公告)日：2001-07-17

申请号：US09257304

申请日：1999-02-25

申请人： Toshiaki Kirihata ,  Gerd Frankowsky

发明人： Toshiaki Kirihata ,  Gerd Frankowsky

IPC分类号： H03K3037

CPC分类号： G11C19/28 ,  G11C7/1048 ,  G11C19/00 ,  H03K19/0963

摘要： A dynamic logic circuit having a charging circuit, comprising a first transistor having a first source/drain electrode adapted for coupling to a voltage supply and a second source/drain electrode connected to a node. The charging circuit couples the voltage supply to the node to place an initial charge on the node. A data transfer circuit is provided comprising a second transistor having a gate adapted for coupling to an input strobe pulse, a first source/drain electrode connected to the node, and a second source/drain electrode responsive to an input data and the input strobe pulse, for transferring the input data to the node to the node such that the pre-charged node is either discharged or remains depending on the input data. An output circuit is responsive to an output strobe pulse for coupling the data at the node to an output. A trailing edge detector of the output strobe pulse detects a time at which the coupling of the data to the output is complete and pre-charges the node at a high level for a subsequent input strobe pulse.

摘要翻译： 一种具有充电电路的动态逻辑电路，包括具有适于耦合到电压源的第一源极/漏极电极和连接到节点的第二源极/漏极电极的第一晶体管。 充电电路将电压源耦合到节点以在节点上放置初始电荷。 提供了一种数据传输电路，包括具有适于耦合到输入选通脉冲的栅极的第二晶体管，连接到该节点的第一源极/漏极电极和响应于输入数据和输入选通脉冲的第二源极/漏极电极 用于将输入数据传送到节点到节点，使得预充电节点根据输入数据被放电或保持。 输出电路响应于输出选通脉冲，用于将节点处的数据耦合到输出。 输出选通脉冲的后沿检测器检测数据到输出的耦合完成的时间，并且为了后续的输入选通脉冲将节点预充电到高电平。

公开(公告)号：US06230290B1

公开(公告)日：2001-05-08

申请号：US08887462

申请日：1997-07-02

申请人： David F. Heidel ,  Wei Hwang ,  Toshiaki Kirihata

发明人： David F. Heidel ,  Wei Hwang ,  Toshiaki Kirihata

IPC分类号： G11C2900

CPC分类号： G11C29/16

摘要： A method of self-programmable Built In Self Test (BIST) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

摘要翻译： 一种用于存储器（例如，动态随机存取存储器（DRAM））的自编程内置自检（BIST）的方法。 可以是DRAM芯片的DRAM包括DRAM内核，微代码或初始命令ROM，BIST引擎，命令寄存器和自编程电路。 在自检期间，BIST引擎可以正常测试DRAM，直到遇到错误。 当遇到错误时，自编程电路在较不严格的条件下重新启动自检程序。 可选地，当DRAM测试无错误时，自编程电路可以在更严格的条件下重新开始测试以确定DRAM功能限制。

公开(公告)号：US06185712B2

公开(公告)日：2001-02-06

申请号：US09109145

申请日：1998-07-02

申请人： Toshiaki Kirihata ,  Christopher Douglas Wait

发明人： Toshiaki Kirihata ,  Christopher Douglas Wait

IPC分类号： G01R3128

CPC分类号： G11C29/026 ,  G11C7/20 ,  G11C11/401 ,  G11C11/4072 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/5004 ,  G11C2207/2254

摘要： An integrated circuit (IC) chip wherein a built-in self test determines the IC's optimum electrical performance. A corresponding optimum performance setting is stored in NVRAM on the chip. Upon each chip power-up, the optimum performance setting is retrieved and provided to chip control which sets the chip for its best performance.

摘要翻译： 集成电路（IC）芯片，其中内置的自检确定了IC的最佳电气性能。 相应的最佳性能设置存储在芯片的NVRAM中。 在每个芯片上电时，检索最佳性能设置并将其提供给芯片控制，从而使芯片达到最佳性能。

公开(公告)号：US6141267A

公开(公告)日：2000-10-31

申请号：US243645

申请日：1999-02-03

申请人： Toshiaki Kirihata ,  Louis Lu-Chen Hsu ,  Chandrasekhar Narayan

发明人： Toshiaki Kirihata ,  Louis Lu-Chen Hsu ,  Chandrasekhar Narayan

IPC分类号： G11C5/02 ,  G11C8/06 ,  G11C11/00 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C11/005 ,  G11C29/846 ,  G11C5/02 ,  G11C8/06

摘要： A defect management engine (DME) for memories integrates a plurality of redundancy data cells and a plurality of redundancy address cells in the same array. The redundancy data cells are used for replacing defective cells in the memories. The redundancy address cells store the addresses of the defective cells. The memories are preferably sub-divided into a plurality of domains. A plurality of defective cells in each domain are supported by a plurality of repair units, each consisting of one or more redundancy data bits and redundancy address bits in the DME. When one or more data bits are read from a domain in the memory, the corresponding wordline in the DME simultaneously activates a plurality of repair units coupling to the wordline (self-contained domain selection). The redundancy data bits and the redundancy address bits are also read from the redundancy data cells and redundancy address cells, respectively. The DME logic detects whether or not the redundancy address bits match or do not match the address inputs of each repair unit (self contained redundancy match detection). This couples either redundancy data bits from the DME (i.e., a matching condition) or the data bits from the domain in the memories (i.e., a no match condition) to the corresponding DQ (self-contained redundancy replacement). The DME enables an integrated redundancy means (self-contained domain selection, self-contained redundancy match detection, and self-contained redundancy replacement). Single bit replacement, multi-bit replacement, line replacement, and variable bit size replacement are discussed. Finally, an extension of the DME concept to a memory system is also discussed.

摘要翻译： 用于存储器的缺陷管理引擎（DME）将多个冗余数据单元和多个冗余地址单元集成在相同的阵列中。 冗余数据单元用于替换存储器中的有缺陷的单元。 冗余地址单元存储有缺陷单元的地址。 存储器优选地被细分为多个域。 每个域中的多个缺陷单元由多个修复单元支持，每个修复单元由DME中的一个或多个冗余数据位和冗余地址位组成。 当从存储器中的域读取一个或多个数据位时，DME中的相应字线同时激活耦合到字线（自包含域选择）的多个修复单元。 冗余数据位和冗余地址位也分别从冗余数据单元和冗余地址单元读取。 DME逻辑检测冗余地址位是否匹配或不匹配每个修复单元的地址输入（自包含冗余匹配检测）。 这将来自DME的冗余数据位（即，匹配条件）或来自存储器中的域的数据位（即，不匹配条件）耦合到相应的DQ（独立冗余替换）。 DME可实现集成的冗余手段（自包含域选择，独立冗余匹配检测和自包含冗余替换）。 讨论了单位替换，多位替换，线替换和可变位大小替换。 最后还讨论了将DME概念扩展到内存系统。

公开(公告)号：US6115310A

公开(公告)日：2000-09-05

申请号：US225343

申请日：1999-01-05

申请人： Dmitry G. Netis ,  L. Brian Ji ,  Toshiaki Kirihata

发明人： Dmitry G. Netis ,  L. Brian Ji ,  Toshiaki Kirihata

IPC分类号： G11C8/08 ,  G11C8/14 ,  G11C8/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/02

CPC分类号： G11C8/18 ,  G11C11/408 ,  G11C11/4091 ,  G11C8/14

摘要： A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.

摘要翻译： 本文公开了一种字线激活延迟监视器电路，其包括位于存储器的数据存储阵列内的采样字线，其中采样字线由存储器内具有基本相同结构或位置的电路​​选择或激活，该电路选择或 激活数据存储阵列的字线。 公开了一种电路，其通过激活位于第二子阵列组的数据存储阵列内的采样字线来确定存储器内的第一子阵列组的字线激活延迟。 还公开了相应的方法。

公开(公告)号：US6038634A

公开(公告)日：2000-03-14

申请号：US17017

申请日：1998-02-02

申请人： L. Brian Ji ,  Toshiaki Kirihata

发明人： L. Brian Ji ,  Toshiaki Kirihata

IPC分类号： G11C11/407 ,  G11C8/10 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G06F12/06

CPC分类号： G11C8/10

摘要： A system is disclosed herein for stabilizing the current dissipation, voltage drop, and heating effects related to accessing blocks within first and second storage units of a double memory unit. The system includes a row selection unit located between the first and second storage units, which accesses storage locations of the first and second storage units according to first and second selection signals conducted from the outer extremities of the double memory unit to selected row locations. The blocks at corresponding distances from the outer extremities are numbered differently such that the sum of lengths of signal travel of the first and second selection signals to the numbered blocks remains relatively constant regardless of the block number which is selected for access.

摘要翻译： 本文公开了一种用于稳定与双存储器单元的第一和第二存储单元内的块访问相关的电流耗散，电压降和加热效应的系统。 该系统包括位于第一和第二存储单元之间的行选择单元，其根据从双存储器单元的外端传输到所选行位置的第一和第二选择信号访问第一和第二存储单元的存储位置。 与外部相对应的距离的块以不同的方式编号，使得第一和第二选择信号到编号的块的信号行程的长度之和保持相对恒定，而不管选择用于访问的块号。

公开(公告)号：US5978931A

公开(公告)日：1999-11-02

申请号：US895061

申请日：1997-07-16

申请人： Toshiaki Kirihata ,  Garbiel Daniel ,  Jean-Marc Dortu ,  Karl-Peter Pfefferl

发明人： Toshiaki Kirihata ,  Garbiel Daniel ,  Jean-Marc Dortu ,  Karl-Peter Pfefferl

IPC分类号： G11C29/44 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/804 ,  G11C29/808

摘要： A fault-tolerant memory device provided with a variable domain redundancy replacement (VDRR) arrangement is described. The memory device includes: a plurality of primary memory arrays; a plurality of domains having at least portions of one domain common to another domain to form an overlapped domain area, and at least one of the domains overlapping portions of at least two of the primary memory arrays; redundancy units, coupled to each of the domains, for replacing faults contained within each of the domains; control circuitry for directing at least one of the faults within one of the domains to be replaced with the redundancy units, wherein at least one other fault of the one domain is replaced by the redundancy unit coupled to another of the domains, if the at least one other fault is positioned within the overlapped domain area. Each redundancy unit supporting the primary memory arrays includes a plurality of redundant elements. Unlike the conventional fixed domain redundancy replacement scheme, RUs are assigned to at least two variable domains, wherein at least a portion of the domain is common to that of another domain. The VDRR makes it possible to choose the most effective domain, and in particular, a smaller domain for repairing a random fault or a larger domain for repairing a clustered faults.

摘要翻译： 描述了具有可变域冗余替换（VDRR）布置的容错存储器件。 存储器件包括：多个主存储器阵列; 多个域具有与另一域共同的一个域的至少部分以形成重叠域区域，并且至少一个域重叠至少两个主存储器阵列的部分; 冗余单元，耦合到每个域，用于替换每个域内包含的故障; 控制电路，用于将要被所述冗余单元替换的所述域内的至少一个故障引导到所述冗余单元，其中所述一个域的至少一个其它故障被耦合到所述域中的另一个的所述冗余单元替换，如果至少 另一个故障位于重叠域区域内。 支持主存储器阵列的每个冗余单元包括多个冗余元件。 与传统的固定域冗余替换方案不同，RU被分配给至少两个可变域，其中域的至少一部分与另一个域的共同。 VDRR使得可以选择最有效的域，特别是用于修复随机故障的较小域或用于修复集群故障的较大域。

公开(公告)号：US5963489A

公开(公告)日：1999-10-05

申请号：US47086

申请日：1998-03-24

申请人： Toshiaki Kirihata ,  John K. DeBrosse ,  Yohji Watanabe ,  Hing Wong

发明人： Toshiaki Kirihata ,  John K. DeBrosse ,  Yohji Watanabe ,  Hing Wong

IPC分类号： G11C29/04 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/806 ,  G11C29/848

摘要： A method and apparatus for repairing a semiconductor memory device. A row redundancy replacement arrangement is provided to repair the memory device consisting of a first plurality of redundant true word lines and a second plurality of redundant complement word lines to simultaneously replace the same first number of first normal word lines and the same second number of the normal complement word lines. An address reordering scheme, preferably implemented as a word line selector circuit and controlled by redundancy control logic and address inputs, allows the redundant true (complement) word lines to replace the normal true (complement) word lines when making the repair. The redundancy replacement arrangement ensures that consistency of the bit map is maintained at all times, irrespective whether the memory device operates in a normal or in a redundancy mode. This approach introduces an added flexibility of incorporating the redundancy replacement without affecting the column access speed.

摘要翻译： 一种用于修复半导体存储器件的方法和装置。 提供行冗余替换布置以修复由第一多个冗余真字字线和第二多个冗余补码字线组成的存储器件，以同时替换相同的第一数量的第一正常字线和相同的第二数目的第 正常补码字线。 地址重排序方案优选地实现为字线选择器电路并由冗余控制逻辑和地址输入控制，允许冗余的真（补）字线在进行修复时替换正常的真（补）字线。 冗余替换布置确保始终保持位图的一致性，而不管存储器件是以正常操作还是以冗余模式操作。 这种方法引入了增加冗余替换的灵活性，而不影响列访问速度。

公开(公告)号：US5831913A

公开(公告)日：1998-11-03

申请号：US825948

申请日：1997-03-31

申请人： Toshiaki Kirihata

发明人： Toshiaki Kirihata

IPC分类号： G11C29/04 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/804 ,  G11C29/808

摘要： A method of making a memory fault-tolerant through the use of a variable size redundancy replacement (VSRR) circuit arrangement. A redundancy array supporting the primary arrays forming the memory includes a plurality of variable size redundancy units, each of which encompassing a plurality of redundant elements. The redundant units used for repairing faults in the memory are independently controlled. All the redundancy elements within a repair unit are preferably replaced simultaneously. The redundancy elements in the redundancy unit are controlled by decoding address lines. The variable size that characterizes this configuration makes it possible to choose the most effective redundancy unit, and in particular, the one most closely fitting the size of the cluster of failures to be replaced. This method significantly reduces the overhead created by added redundancy elements and control circuitry, while improving the access speed and reducing power consumption. Finally, a fault-tolerant block redundancy controlled by a priority decoder makes it possible to use VSRR units for repairing faults in the block redundancy prior to its use for replacing a defective block within the memory.

摘要翻译： 通过使用可变尺寸冗余替换（VSRR）电路布置来使存储器容错的方法。 支持形成存储器的主阵列的冗余阵列包括多个可变大小的冗余单元，每个冗余单元包括多个冗余元件。 用于修复存储器故障的冗余单元是独立控制的。 维修单元内的所有冗余元件优选同时更换。 冗余单元中的冗余元件通过解码地址线来控制。 表征此配置的可变大小使得可以选择最有效的冗余单元，特别是最接近要替换的故障群集大小的冗余单元。 该方法显着降低了增加冗余元件和控制电路所产生的开销，同时提高了访问速度并降低了功耗。 最后，由优先级解码器控制的容错块冗余使得可以使用VSRR单元来修复块冗余中的故障，在其用于替换存储器内的有缺陷块之前。

公开(公告)号：US5745431A

公开(公告)日：1998-04-28

申请号：US583263

申请日：1996-01-05

申请人： Dale Edward Pontius ,  Steven William Tomashot ,  Toshiaki Kirihata ,  Robert Henry Kruggel

发明人： Dale Edward Pontius ,  Steven William Tomashot ,  Toshiaki Kirihata ,  Robert Henry Kruggel

IPC分类号： G11C8/18 ,  G11C8/00

CPC分类号： G11C8/18

摘要： An address decode circuit for receiving address input signals, includes a device for detecting a change in the address input signals, and a device for generating a control signal in response to a detected change in the address input signals. A gating mechanism gates at least one address bit in the address input signals input to the address decode circuit with the control signal.

摘要翻译： 一种用于接收地址输入信号的地址解码电路，包括用于检测地址输入信号变化的装置，以及响应于所检测到的地址输入信号的变化而产生控制信号的装置。 选通机构通过控制信号将输入到地址解码电路的地址输入信号中的至少一个地址位置1。