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公开(公告)号：US11340572B1
公开(公告)日：2022-05-24
申请号：US17100510
申请日：2020-11-20
Applicant: Dell Products L.P.
Inventor： Timothy M. Lambert , Michael J. Stumpf , Nihit S. Bhavsar , Jeffrey L. Kennedy
IPC: G08B1/08 , G05B19/042 , F24F11/30 , F24F11/58 , F24F11/72 , F24F11/65 , H04L12/28 , G08B25/06 , H04L67/12
Abstract: An information handling system may include an air mover configured to drive a flow of air and a processing component communicatively coupled to the air mover for controlling operation of the air mover via a first wire configured to communicate analog air mover speed commands from the processing component to the air mover for controlling a speed of the air mover and a second wire configured to communicate analog tachometer information from the air mover to the processing component. At least one of the air mover and the processing component may be configured to initiate a mode for serial digital communication via the first wire and the second wire. The air mover and the processing component may be configured to communicate information to each other in accordance with a digital communication protocol via the first wire and the second wire during the mode for serial digital communication.
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公开(公告)号：US20220155834A1
公开(公告)日：2022-05-19
申请号：US16952467
申请日：2020-11-19
Applicant: Dell Products L.P.
Inventor： Jeffrey L. Kennedy , Timothy M. Lambert , Yuchen Xu
Abstract: Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.
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公开(公告)号：US11249935B1
公开(公告)日：2022-02-15
申请号：US17142944
申请日：2021-01-06
Applicant: Dell Products L.P.
Inventor： Timothy M. Lambert , Shawn J. Dube
Abstract: A system may include a first device and a second device communicatively coupled to the first device via a communications bus, wherein the communications bus comprises a single clock line for transmission of a clock signal from the first device to the second device, a single frame line for transmission of a frame alignment signal from the first device to the second device, and at least one communications channel for serialized communication of payloads of data between the first device and the second device, wherein the payloads of data have at least two different latencies.
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公开(公告)号：US11093422B2
公开(公告)日：2021-08-17
申请号：US16741361
申请日：2020-01-13
Applicant: Dell Products L.P.
Inventor： Timothy M. Lambert , Hendrich M. Hernandez , Yogesh Varma , Kurtis John Bowman , Shyamkumar T. Iyer , John Christopher Beckett
Abstract: A processor/endpoint communication coupling configuration system includes a plurality of processing subsystems coupled to a multi-endpoint adapter device by a plurality of communication couplings included on at least one hardware subsystem. A communication coupling configuration engine identifies each at least one hardware subsystem, determines at least one communication coupling configuration capability of the plurality of communication couplings, and determines at least one first multi-endpoint adapter device capability of the multi-endpoint adapter device. The communication coupling configuration engine then configures the plurality of communication couplings based on the at least one hardware subsystem, the at least one communication configuration capability, and the at least one first multi-endpoint adapter device capability in order to provide at least one communication resource between at least one of the plurality of processing subsystems and at least one endpoint on the first multi-endpoint adapter device.
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公开(公告)号：US20210232176A1
公开(公告)日：2021-07-29
申请号：US16775963
申请日：2020-01-29
Applicant: Dell Products L.P.
Inventor： Isaac Q. Wang , Timothy M. Lambert
Abstract: An information handling system includes a synchronizer and a module identifier. The module identifier identifies a module identification event for a module attached to the information handling system; in response to identifying the module identification event: obtains a module identifier from the module, and makes a determination that the module identifier indicates that the module is a synchronization type of module, and initiates, based on the determination, time synchronization for the information handling system with a second information handling system using the module and the synchronizer.
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Patent Agency Ranking
公开(公告)号：US20210081214A1
公开(公告)日：2021-03-18
申请号：US16572705
申请日：2019-09-17
Applicant: Dell Products L.P.
Inventor： Timothy M. Lambert , Isaac Q. Wang , Shawn Dube , Johan Rahardjo
IPC: G06F9/4401
Abstract: Methods, systems, and computer programs encoded on computer storage medium, for receiving a request to switch a mode of an information handling system (IHS) from a multi-socket mode to a multi-single socket mode; in response to receiving the request, placing each socket of the IHS in an auxiliary power state independent of each other; after placing each socket of the IHS in the auxiliary power state, altering parameters of the sockets of the IHS, including: altering CPU straps, power sequencing, reset sequencing, and bus re-direction associated with one or more of the sockets of the IHS; and in response to altering the parameters of the sockets of the IHS, switching the mode of the IHS from the multi-socket mode to the multi-single socket mode such that a processor for each socket is a bootstrap processor.
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公开(公告)号：US10922150B2
公开(公告)日：2021-02-16
申请号：US15803277
申请日：2017-11-03
Applicant: Dell Products L.P.
Inventor： Timothy M. Lambert , Jeffrey Kennedy
Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a host system comprising at least one processor, a management controller communicatively coupled to the at least one processor and configured to provide out-of-band management of the information handling system, a debugging circuit, and a logic device coupled to the host system and to the management controller. The logic device may be configured to determine that a trigger event has taken place, and in response to the trigger event, provide a serial data stream corresponding to the trigger event to the debugging circuit. The debugging circuit may be configured to provide access to the serial data stream to a debugging information handling system via a wireless interface.
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公开(公告)号：US20200341929A1
公开(公告)日：2020-10-29
申请号：US16395584
申请日：2019-04-26
Applicant: Dell Products L.P.
Inventor： Timothy M. Lambert , Yogesh Varma
Abstract: A multi-endpoint device sideband communication system includes a board including a board sideband communication subsystem coupled to a connector on the board. A multi-endpoint adapter device is connected to the board via the connector, and includes an adapter sideband communication subsystem connected to the connector via a first set of adapter sideband connections, and to each of a plurality of endpoint devices included on the multi-endpoint adapter device via respective second sets of adapter sideband communication connections. The adapter sideband communication subsystem receives a first sideband communication from the board sideband communication subsystem via the connector and, based on a first sideband communication policy stored in the adapter sideband communication subsystem, provides the first sideband communication to at least one of the plurality of endpoint devices via each respective second set of adapter sideband communication connections connected to that endpoint device.
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公开(公告)号：US10599523B2
公开(公告)日：2020-03-24
申请号：US15801879
申请日：2017-11-02
Applicant: Dell Products L.P.
Inventor： Timothy M. Lambert , Michael J. Stumpf , Ronald Paul Rudiak
Abstract: An information handling system may include at least one processor, a management controller, a serial peripheral interface (SPI) read-only memory (ROM), and at least one logic device. The management controller may be communicatively coupled to the at least one processor and configured to provide out-of-band management of the information handling system. The logic device may be configured to reset the SPI ROM in response to an indication that the SPI ROM is to be reset, and the resetting may include detaching the SPI ROM from a SPI controller, disconnecting a power source from the SPI ROM, in response to a passage of a particular amount of time, reconnecting the power source to the SPI ROM, and re-attaching the SPI ROM to the SPI controller.
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公开(公告)号：US20190390864A1
公开(公告)日：2019-12-26
申请号：US16017222
申请日：2018-06-25
Applicant: Dell Products L.P.
Inventor： Timothy M. Lambert , Sandor T. Farkas , Robert B. Curtis
Abstract: Systems and methods for fan typing and anomaly detection may provide a pulse width modulation (PWM) control signal with a predetermined threshold duty cycle to a fan, receive a tachometer signal from the fan while the PWM control signal has the threshold duty cycle, and compare the frequency of the tachometer signal (expressed in revolutions per minute) to an expected tachometer frequency for fans of a first fan type with the PWM control signal having the threshold duty cycle, according to an RPM vs. PWM curve specified for fans of the first fan type. The systems and methods may determine, based on the comparison, that the fan is of the first fan type and provide an indication that the fan is of the first fan type to a fan controller. Deviations from expected tachometer responses may indicate an anomaly, such as an actual fan failure or a predicted fan failure.
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