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    Decoder with memory
    62.
    发明授权
    Decoder with memory 有权
    内存解码器

    公开(公告)号：US07738314B2

    公开(公告)日：2010-06-15

    申请号：US12108258

    申请日：2008-04-23

    Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

    Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

    IPC: G11C8/00

    CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

    Abstract: In one embodiment, a decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes: a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true; a (n+1)th switch coupling the dynamic OR node to ground, the (n+1)th switch being controlled such that it turns on if the dynamic OR node is charged, whereby the pre-charged dynamic OR node discharges if the dynamic OR node remains charged; an odd plurality of inverters coupled in series with the dynamic OR node; and a word line driven by the odd plurality of inverters.

    Abstract translation: 在一个实施例中，提供一种解码器，用于解码具有从第一地址位a1到最后地址位aN的多个位的地址，每个地址位是真或假，其包括：预充电电路，其适于预先 充电动态NOR节点和动态OR节点，然后允许预充电动态NOR节点和预充电动态OR节点浮动; 耦合在动态NOR节点和地之间的多个开关，每个开关唯一地对应于地址位，使得开关的范围从对应于a1的第一开关到对应于aN的第n个开关，其中对应于真地址位 被配置为仅当其对应的地址位为假时才导通，并且其中对应于假地址位的任何开关被配置为仅在其对应的地址位为真时才导通; 第（n + 1）个开关将动态OR节点耦合到地，第（n + 1）个开关被控制，使得如果动态OR节点被充电，其导通，由此如果 动态OR节点保持充电; 与动态OR节点串联耦合的奇数个反相器; 以及由奇数个反相器驱动的字线。

    Block-by-block leakage control and interface
    63.
    发明授权
    Block-by-block leakage control and interface 有权
    逐块泄漏控制和接口

    公开(公告)号：US07728621B2

    公开(公告)日：2010-06-01

    申请号：US12144622

    申请日：2008-06-23

    Applicant: Esin Terzioglu ,  Gil I. Winograd

    Inventor： Esin Terzioglu ,  Gil I. Winograd

    IPC: H03K17/16 ,  H03K19/003

    CPC classification number: H03K19/0016

    Abstract: In one embodiment, a method of leakage control for a memory having an array of memory cells arranged into a plurality of sub-arrays is provided wherein each sub-array has a sleep mode of operation controlled by a sleep signal in which stored data is lost, and wherein each sub-array asserts a local clock if the sub-array is addressed. The method includes the act of asserting a sleep signal while addressing a given one of the sub-arrays such that only the given one of the sub-arrays is placed into the sleep mode.

    Abstract translation: 在一个实施例中，提供了一种具有布置成多个子阵列的存储器单元阵列的存储器的泄漏控制方法，其中每个子阵列具有由存储数据丢失的睡眠信号控制的休眠模式 ，并且其中如果子阵列被寻址，则每个子阵列断言本地时钟。 该方法包括在寻址给定的一个子阵列的同时确定休眠信号的动作，使得仅将给定的一个子阵列置于睡眠模式。

    MULTI-PORT SRAM WITH SIX-TRANSISTOR MEMORY CELLS
    64.
    发明申请
    MULTI-PORT SRAM WITH SIX-TRANSISTOR MEMORY CELLS 有权
    具有六极晶体管存储器单元的多端口SRAM

    公开(公告)号：US20090190389A1

    公开(公告)日：2009-07-30

    申请号：US12258231

    申请日：2008-10-24

    Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

    Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

    IPC: G11C11/00 ,  G11C8/16

    CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

    Abstract: In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals; an input multiplexer to select from the input registers to provide a selected input signal to the 6-T SRAM's single input port; a plurality of output registers corresponding to a plurality of output ports to register corresponding output signals; and an output de-multiplexer to select from the output registers to provide an output signal from the 6-T SRAM's single output port to the selected output register.

    Abstract translation: 在一个实施例中，提供了多端口SRAM，其包括：单个输入端口和输出端口6-T SRAM; 以及多端口控制块电路，其包括：对应于多个输入端口的多个输入寄存器，用于寄存对应的输入信号; 输入多路复用器，用于从输入寄存器中选择以向6-T SRAM的单个输入端口提供选定的输入信号; 对应于多个输出端口的多个输出寄存器，用于寄存对应的输出信号; 以及输出解复用器，从输出寄存器中选择，以提供从6-T SRAM单输出端口到所选输出寄存器的输出信号。

    One-time-programmable memory
    65.
    发明授权
    One-time-programmable memory 有权
    一次可编程存储器

    公开(公告)号：US07508694B2

    公开(公告)日：2009-03-24

    申请号：US11747390

    申请日：2007-05-11

    Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

    Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

    IPC: G11C17/16

    CPC classification number: G11C17/16

    Abstract: A one-time-programmable memory cell uses two complementary antifuses that are programmed in a complementary fashion such that only one of the two complementary antifuses is stressed by a programming voltage. The programming voltage stress one a particular one of the complementary antifuses indicates a logical state of the memory cell. For example, a logical high state may correspond to a first one of the complementary antifuses being stressed whereas a logical low state may correspond to the stressing of the remaining one of the complementary antifuses.

    Abstract translation: 一次性可编程存储器单元使用以互补方式编程的两个互补反熔丝，使得仅两个互补反熔丝中的仅一个被编程电压施加。 补充反熔丝中的特定一个的编程电压应力指示存储器单元的逻辑状态。 例如，逻辑高状态可以对应于被应力的互补反熔丝中的第一个，而逻辑低状态可以对应于剩余的一个互补反熔丝的应力。

    Software programmable verification tool having multiple built-in self-test (BIST) modules for testing and debugging multiple devices under test (DUT)
    66.
    发明授权
    Software programmable verification tool having multiple built-in self-test (BIST) modules for testing and debugging multiple devices under test (DUT) 有权
    具有多个内置自检（BIST）模块的软件可编程验证工具，用于测试和调试多个待测器件（DUT）

    公开(公告)号：US07464295B2

    公开(公告)日：2008-12-09

    申请号：US10269635

    申请日：2002-10-11

    Applicant: Zevnep M. Toros ,  Esin Terzioglu ,  Gil Winograd

    Inventor： Zevnep M. Toros ,  Esin Terzioglu ,  Gil Winograd

    IPC: G06F11/00

    CPC classification number: G06F11/27 ,  G01R31/31705 ,  G01R31/318555 ,  G11C29/16 ,  G11C2029/0401

    Abstract: Aspects of the invention may include testing and debugging an embedded device under test. Testing and debugging and embedded device under test may include the step of loading an instruction into a parameterized shift register of each one of a plurality of BIST modules coupled to an individual one of a plurality of embedded memory modules comprising the embedded device under test. An identity of each of the instruction loaded into the parameterized shift register of each one of the plurality of BIST modules may subsequently be determined. A separate test signal may be generated from each one of the plurality of BIST modules corresponding to the determined identity of the instruction loaded in each one of the plurality of BIST modules, each one of the generated test signals causing control and execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules comprising the embedded device under test.

    Abstract translation: 本发明的方面可以包括测试和调试被测设备。 测试和调试以及被测试嵌入式设备可以包括将指令加载到多个BIST模块中的每个BIST模块的参数化移位寄存器中的步骤，所述BIST模块耦合到包括被测嵌入式设备的多个嵌入式存储器模块中的单独一个。 可以随后确定加载到多个BIST模块中的每一个的参数化移位寄存器中的每个指令的身份。 可以从多个BIST模块中的每个BIST模块生成对应于所确定的多个BIST模块中的每个BIST模块中加载的指令的身份的单独的测试信号，每个生成的测试信号引起测试的控制和执行， 包括被测嵌入式设备的多个嵌入式存储器模块中的每一个的对应的一个的调试。

    MEMORY ROW AND COLUMN REDUNDANCY
    69.
    发明申请
    MEMORY ROW AND COLUMN REDUNDANCY 有权
    记忆线和列的冗余

    公开(公告)号：US20080225613A1

    公开(公告)日：2008-09-18

    申请号：US12016738

    申请日：2008-01-18

    Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

    Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C29/789

    Abstract: In one embodiment, a memory includes a row and/or column redundancy architecture that uses binary cells to indicate whether a given row or column of memory cells is faulty. The binary cell is adapted to store a “repair true” signal in response to a conventional access to the corresponding row or column and also the assertion of a set signal.

    Abstract translation: 在一个实施例中，存储器包括使用二进制单元来指示给定行或列的存储器单元是否有故障的行和/或列冗余体系结构。 二进制单元适于存储响应于对相应行或列的常规访问以及设置信号的断言的“修复真实”信号。

    INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT
    70.
    发明申请
    INTEGRATED CIRCUITS WITH REDUCED LEAKAGE CURRENT 审中-公开
    具有降低漏电流的集成电路

    公开(公告)号：US20080224729A1

    公开(公告)日：2008-09-18

    申请号：US11857133

    申请日：2007-09-18

    Applicant: Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

    Inventor： Morteza Afghahi ,  Esin Terzioglu ,  Gil I. Winograd

    IPC: H03K17/16

    CPC classification number: H03K19/0016

    Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

    Abstract translation: 在一个实施例中，NMOS晶体管的源极耦合到公共源节点，使得如果公共源节点接地，则NMOS晶体管导通泄漏电流。 为了减少漏电流，公共源节点处于潜在状态。 类似地，PMOS晶体管的源极耦合到公共源节点，使得如果公共源节点被充电到电源电压VDD，则PMOS晶体管传导泄漏电流。 为了减少漏电流，公共源节点的电位降低。

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