公开(公告)号：US6078082A

公开(公告)日：2000-06-20

申请号：US893628

申请日：1997-07-11

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76

CPC classification number: H01L29/66659 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1045 ,  H01L29/7835

Abstract: An asymmetric insulated-gate field-effect transistor is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone contains a main portion and more lightly doped extension that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa. In fabricating complementary versions of the transistor, the threshold body zone of one transistor can be formed at the same time as the drain extension of a complementary transistor, and vice versa.

Abstract translation: 非对称绝缘栅场效应晶体管被配置在不对称的轻掺杂漏极结构中，其减轻热载流子效应，并使源极特性与漏极特性去耦合。 晶体管具有形成有与漏极区相邻的输出部分和与源极区相邻的更重掺杂的输入部分的多部分通道。 漏极区域包含主要部分和更轻的掺杂延伸部分，其与输出通道部分相吻合。 漏极延伸部至少与主漏极部分的上半导体表面一样远，以帮助减少热载流子效应。 输入通道部分位于阈值体区，其掺杂确定阈值电压。 重要的是，避免了提供轻掺杂的源延伸，从而改善漏极特性不会损害源特性，反之亦然。 在制造晶体管的互补版本时，可以在互补晶体管的漏极延伸的同时形成一个晶体管的阈值体区，反之亦然。

公开(公告)号：US6020227A

公开(公告)日：2000-02-01

申请号：US812509

申请日：1997-03-07

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/337

CPC classification number: H01L29/66659 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1045

Abstract: A structure containing multiple field-effect transistors (60 and 150) is fabricated from a semiconductor body having material (82) of a specified conductivity type. Semiconductor dopant of the specified conductivity type is introduced, typically simultaneously, (a) into part of a first channel zone of the material of the specified conductivity type to define a threshold channel portion (66) more heavily doped than a main channel portion (65) and (b) into substantially all of a second channel zone of the material of the specified conductivity type. First and second gate electrodes (69 and 141) are provided respectively above, and insulatingly spaced apart from, the first and second channel zones. Semiconductor dopant of the opposit conductivity type is introduced into the semiconductor body to define (a) a pair of first source/drain zones (63/64 and 75/76) laterally separated by the first channel zone and (b) a pair of second source/drain zones (133/134 and 135/136) laterally separated by the second channel zone.

Abstract translation: 包含多个场效应晶体管（60和150）的结构由具有指定导电类型的材料（82）的半导体主体制成。 特定导电类型的半导体掺杂剂通常同时引入（a）为特定导电类型的材料的第一沟道区的一部分，以限定比主沟道部分（65）更重掺杂的阈值沟道部分（66） ）和（b）成为特定导电类型的材料的基本上所有的第二通道区。 分别设置有第一和第二栅电极（69和141），并且与第一和第二通道区隔开间隔开。 将相对导电类型的半导体掺杂剂引入半导体本体中以限定（a）由第一沟道区横向分离的一对第一源极/漏极区（63/64和75/76）和（b）一对第二沟道区 源极/漏极区（133/134和135/136）由第二通道区横向隔开。

公开(公告)号：US5952701A

公开(公告)日：1999-09-14

申请号：US912053

申请日：1997-08-18

Applicant: Constantin Bulucea ,  Daniel C. Kerr

Inventor： Constantin Bulucea ,  Daniel C. Kerr

IPC: H01L27/092 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC classification number: H01L27/092

Abstract: A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.

Abstract translation: 由半导体材料体（102和104）产生一对互补CJIGFET（100和160）。 每个CJIGFET形成有（a）沿着半导体主体的上表面定位的一对横向分离的源极/漏极区（112和114或172和174），（b）沟槽区（110或170） 源极/漏极区，和（c）覆盖并且与沟道区电绝缘的栅电极（118或178）。 每个CJIGFET的栅电极在半导体材料的能带隙的中间具有0.3ev以内的费米能级。 一个晶体管通常根据场致感沟道模式导通电流，而另一晶体管根据冶金通道模式导通电流。 每个CJIGFET的阈值电压幅值通常不超过0.5 V.

公开(公告)号：US5744372A

公开(公告)日：1998-04-28

申请号：US456454

申请日：1995-06-01

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66659 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1045 ,  H01L29/7835

Abstract: Each of a pair of complementary insulated-gate field-effect transistors is manufactured in an asymmetric lightly doped drain structure that enables the source characteristics to be decoupled from the drain characteristics. Each transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone of each transistor contains a main portion and a more lightly doped extension that meets the output channel portion. The drain extension of each transistor typically extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion of each transistor is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of lightly doped source extensions is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa. In fabricating the complementary transistor structure, the threshold body zone of each transistor is formed at the same time as the drain extension of the other transistor.

Abstract translation: 一对互补绝缘栅场效应晶体管中的每一个以不对称的轻掺杂漏极结构制造，使源极特性能够与漏极特性去耦合。 每个晶体管具有形成有与漏极区相邻的输出部分和与源极区相邻的更重掺杂的输入部分的多部分通道。 每个晶体管的漏极区域包含一个主要部分和一个更轻的掺杂的扩展部分，其与输出通道部分相吻合。 每个晶体管的漏极延伸通常至少与主漏极部分的上半导体表面一样远，以帮助减少热载流子效应。 每个晶体管的输入通道部分位于阈值体区，其掺杂确定阈值电压。 重要的是，避免了提供轻掺杂的源延伸，从而改善漏极特性不会损害源特性，反之亦然。 在制造互补晶体管结构时，每个晶体管的阈值体区与另一个晶体管的漏极延伸同时形成。

公开(公告)号：US5698459A

公开(公告)日：1997-12-16

申请号：US456446

申请日：1995-06-01

Applicant: Michael J. Grubisich ,  Constantin Bulucea

Inventor： Michael J. Grubisich ,  Constantin Bulucea

IPC: H01L21/331 ,  H01L29/08 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L29/0804 ,  H01L29/0821 ,  Y10S148/01

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract translation: 垂直双极晶体管的发射极和基极的一部分与场隔离区相邻以形成壁 - 发射极结构。 该晶体管在集电极和任选地在基极中具有额外的掺杂。 沿着本征基底下方的集电极 - 基极结提供额外的集电极掺杂，以产生与场隔离区域横向分开的特殊集电区。 特殊收集器区域的存在导致本征基极更薄，从而提高截止频率和总体电流增益。 沿着场隔离区域在本征基极中提供额外的基极掺杂以提高晶体管的击穿电压和漏电流特性。

公开(公告)号：US5589409A

公开(公告)日：1996-12-31

申请号：US393647

申请日：1995-02-24

Applicant: Constantin Bulucea ,  Michael J. Grubisich

Inventor： Constantin Bulucea ,  Michael J. Grubisich

IPC: H01L21/331 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  Y10S148/01

Abstract: A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with a pair of more lightly doped base portions that encroach substantially into the intrinsic base below the main intrinsic base portion. The two deep encroaching base portions extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced. Manufacture of the transistor entails introducing suitable dopants into a semiconductor body. In one fabrication process, a fast-diffusing dopant is employed in forming the deep encroaching base portions without significantly affecting earlier-created transistor regions.

Abstract translation: 利用特殊的二维本征基极掺杂分布来改善其本征基极包括主本征部分的垂直双极晶体管的输出电流 - 电压特性。 特殊的掺杂分布通过一对更轻掺杂的基底部分实现，其基本上侵入主本征基底部下方的本征基底。 两个深侵入基部分彼此充分地相互延伸，以建立通常提高穿通电压幅度的二维电荷共享机构。 从而提高了晶体管的电流 - 电压特性。 晶体管的制造需要将合适的掺杂剂引入半导体本体。 在一个制造工艺中，快速扩散掺杂剂用于形成深入侵基底部分，而不会明显影响早期产生的晶体管区域。

公开(公告)号：US5581115A

公开(公告)日：1996-12-03

申请号：US319759

申请日：1994-10-07

Applicant: Michael J. Grubisich ,  Constantin Bulucea

Inventor： Michael J. Grubisich ,  Constantin Bulucea

IPC: H01L21/331 ,  H01L29/08 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70

CPC classification number: H01L29/66272 ,  H01L29/0804 ,  H01L29/0821 ,  Y10S148/01

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract translation: 垂直双极晶体管的发射极和基极的一部分与场隔离区相邻以形成壁 - 发射极结构。 该晶体管在集电极和任选地在基极中具有额外的掺杂。 沿着本征基底下方的集电极 - 基极结提供额外的集电极掺杂，以产生与场隔离区域横向分开的特殊集电区。 特殊收集器区域的存在导致本征基极更薄，从而提高截止频率和总体电流增益。 沿着场隔离区域在本征基极中提供额外的基极掺杂以提高晶体管的击穿电压和漏电流特性。

公开(公告)号：US5548158A

公开(公告)日：1996-08-20

申请号：US300498

申请日：1994-09-02

Applicant: Constantin Bulucea ,  Michael J. Grubisich

Inventor： Constantin Bulucea ,  Michael J. Grubisich

IPC: H01L21/331 ,  H01L29/10 ,  H01L27/082 ,  H01L27/102 ,  H01L29/00

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  Y10S148/01

Abstract: A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with a pair of more lightly doped base portions that encroach substantially into the intrinsic base below the main intrinsic base portion. The two deep encroaching base portions extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced.

Abstract translation: 利用特殊的二维本征基极掺杂分布来改善其本征基极包括主本征部分的垂直双极晶体管的输出电流 - 电压特性。 特殊的掺杂分布通过一对更轻掺杂的基底部分实现，其基本上侵入主本征基底部下方的本征基底。 两个深侵入基部分彼此充分地相互延伸，以建立通常提高穿通电压幅度的二维电荷共享机构。 从而提高了晶体管的电流 - 电压特性。

公开(公告)号：US5410170A

公开(公告)日：1995-04-25

申请号：US47723

申请日：1993-04-14

Applicant: Constantin Bulucea ,  Rebecca Rossen

Inventor： Constantin Bulucea ,  Rebecca Rossen

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0696 ,  H01L29/1095 ,  H01L29/7813 ,  H01L29/7802

Abstract: Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well.

Abstract translation: 公开了两个拓扑不同的单元，其减少了每个器件的总触点数，并且适用于中高压DMOS晶体管。 这些细胞使用源和身体之间的集成连接，使得它们对于通过颗粒污染或光刻缺陷接触接触不那么敏感。 这些拓扑结构包括细长的六角形细胞或埋深体细胞。 两个电池在高电流中压沟槽DMOS晶体管中是最有效的，其中身体接触的密度变得过高，而周边/面积几何因子不太重要。 所公开的实施例是DMOS结构的沟槽类型。 然而，这些单元也可以在平面DMOS晶体管中实现。

公开(公告)号：US08513703B2

公开(公告)日：2013-08-20

申请号：US12908514

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L21/338 ,  H01L29/778

CPC classification number: H01L29/0661 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: The Si substrate of a group III-N HEMT is formed in layers that define a p-n junction which electrically isolates an upper region of the Si substrate from a lower region of the Si substrate. As a result, the upper region of the Si substrate can electrically float, thereby obtaining a full buffer breakdown voltage, while the lower region of the Si substrate can be attached to a package by way of a conductive epoxy, thereby significantly improving the thermal conductivity of the group III-N HEMT and minimizing undesirable floating-voltage regions.

Abstract translation: 组III-N HEMT的Si衬底形成为限定将Si衬底的上部区域与Si衬底的下部区域电隔离的p-n结的层。 结果，Si衬底的上部区域可以电浮动，从而获得全缓冲击穿电压，而Si衬底的下部区域可以通过导电环氧树脂附着到封装上，从而显着提高导热性 的III-N HEMT组，并且使不期望的浮动电压区域最小化。