公开(公告)号：US20220029000A1

公开(公告)日：2022-01-27

申请号：US16934669

申请日：2020-07-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Siva P. Adusumilli ,  Vibhor Jain ,  Steven Bentley

IPC: H01L29/66 ,  H01L29/20

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. A layer stack is formed on a semiconductor substrate comprised of a single-crystal semiconductor material. The layer stack includes a semiconductor layer comprised of a III-V compound semiconductor material. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer extends laterally beneath the layer stack.

公开(公告)号：US20210376159A1

公开(公告)日：2021-12-02

申请号：US16890063

申请日：2020-06-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Mark Levy ,  Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L21/763

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

公开(公告)号：US11107884B2

公开(公告)日：2021-08-31

申请号：US16538062

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Anthony K. Stamper ,  Laura J. Silverstein ,  Cameron E. Luce

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.

公开(公告)号：US20210217874A1

公开(公告)日：2021-07-15

申请号：US17214969

申请日：2021-03-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/737 ,  H01L21/762

Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the collector region.

公开(公告)号：US11063140B2

公开(公告)日：2021-07-13

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L27/082

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US20210111063A1

公开(公告)日：2021-04-15

申请号：US16598064

申请日：2019-10-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Ian McCallum-Cook ,  Michel J. Abou-Khalil

IPC: H01L21/763 ,  H01L29/06 ,  H01L23/66 ,  H01L21/265 ,  H01L21/324

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.

公开(公告)号：US20210098612A1

公开(公告)日：2021-04-01

申请号：US16784683

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Pekarik ,  Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Herbert Ho ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first heterojunction bipolar transistor includes a first emitter, a first collector, and a first base layer having a portion positioned between the first emitter and the first collector. A second heterojunction bipolar transistor includes a second emitter, a second collector, and a second base layer having a portion positioned between the second emitter and the second collector. The first and second base layers each comprise silicon-germanium, the first base layer includes a first germanium profile, and the second base layer includes a second germanium profile that is identical to the first germanium profile.

公开(公告)号：US11639895B2

公开(公告)日：2023-05-02

申请号：US17195887

申请日：2021-03-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik ,  Yusheng Bian

IPC: G01N21/64 ,  G01N21/85 ,  H01L31/0232 ,  H01L31/12 ,  H01L31/02

Abstract: A “lab on a chip” includes an optofluidic sensor and components to analyze signals from the optofluidic sensor. The optofluidic sensor includes a substrate, a channel at least partially defined by a portion of a layer of first material on the substrate, input and output fluid reservoirs in fluid communication with the channel, at least a first radiation source coupled to the substrate adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent and below the channel.

公开(公告)号：US20230125886A1

公开(公告)日：2023-04-27

申请号：US17506992

申请日：2021-10-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N.R. Vanukuru ,  Mark Levy

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

公开(公告)号：US20230114096A1

公开(公告)日：2023-04-13

申请号：US17450186

申请日：2021-10-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01Q1/22 ,  H01L29/08

Abstract: An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.