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61.发明授权
公开(公告)号：US4240138A
公开(公告)日：1980-12-16
申请号：US948284
申请日：1978-10-03
申请人： Gerard Chauvel
发明人： Gerard Chauvel
CPC分类号： G06F13/1673 , G06F13/287
摘要： System for direct access to a memory associated with a microprocessor data processing device comprising a direct access interface for introducing or extracting data in the memory during interruptions of the connection between the processing device and the memory, and a buffer interface operable during a portion of the access time of the processing device to the memory, to supply data addresses contained in the memory originating from the processing device and to enable circulation of corresponding data between the processing device and the memory, and during the remainder of the access time of the processing device, to the end of the access time, to store data transferred from the memory and to prevent transmission of data to the memory. A logic circuit controls inhibition of the buffer interface or of the direct access interface and, during the periods of inhibition of the buffer interface, permits the circulation of data and of addresses between the direct access interface and the memory.
摘要翻译： 用于直接访问与微处理器数据处理设备相关联的存储器的系统，包括用于在处理设备和存储器之间的连接中断期间在存储器中引入或提取数据的直接访问接口，以及可在一部分 提供处理设备到存储器的访问时间，以提供包含在来自处理设备的存储器中的数据地址，并且能够在处理设备和存储器之间以及在处理设备的访问时间的剩余时间期间循环相应的数据 在访问时间结束时，存储从存储器传送的数据并防止数据传送到存储器。 逻辑电路控制对缓冲器接口或直接访问接口的禁止，并且在缓冲器接口的禁止期间允许在直接访问接口和存储器之间的数据和地址的循环。
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公开(公告)号：US08185666B2
公开(公告)日：2012-05-22
申请号：US11116522
申请日：2005-04-28
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between the contents of the first register and a predetermined value. The instruction is particularly useful for determining whether an attempted access (either a load or write) to an array improperly targets a location outside the boundary of the array. In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.
摘要翻译： 处理器执行使得在第一寄存器的内容和第二寄存器的内容之间以及第一寄存器的内容与预定值之间执行比较的指令。 该指令对于确定对阵列的尝试访问（加载或写入）是否不正确地定位到阵列边界外的位置特别有用。 在一些实施例中，系统（例如，诸如蜂窝电话的通信设备）包括能够执行如上所述的指令的处理器。
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公开(公告)号：US07930689B2
公开(公告)日：2011-04-19
申请号：US11186271
申请日：2005-07-21
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.
摘要翻译： 提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。 在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。 软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。 其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件， 其中所述存储器元件未映射到所述处理器的数据存储器空间。
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公开(公告)号：US07533250B2
公开(公告)日：2009-05-12
申请号：US11188311
申请日：2005-07-25
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.
摘要翻译： 一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。 处理器还包括耦合到解码逻辑的第二存储单元。 解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则处理一组指令来代替单个指令，其中单个指令需要操作数。 如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，修改操作数，并将操作数存储到第二存储单元以供指令组使用。
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公开(公告)号：US07395413B2
公开(公告)日：2008-07-01
申请号：US10631585
申请日：2003-07-31
申请人： Gerard Chauvel
发明人： Gerard Chauvel
IPC分类号： G06F9/30
CPC分类号： G06F9/30134 , G06F9/3001 , G06F9/30065 , G06F9/30101 , G06F9/30174 , G06F9/325 , G06F9/3836 , G06F9/3885 , G06F12/0253 , G06F12/0804 , G06F12/0891 , G06F12/126 , G06F2212/502
摘要： A processor (e.g., a co-processor) capable of executing instructions sequentially, comprises at least two functional hardware resources. When two instructions that are consecutive in program order and are executed on two separate functional hardware resources, the execution of the two instructions may be parallelized if the two instructions are within a hardware loop. The processor thus, may implement a multiply and accumulate process in an efficient manner by performing the multiply instructions concurrently with the add instructions (which require fewer cycles to complete than the multiply instructions).
摘要翻译： 能够顺序执行指令的处理器（例如，协处理器）包括至少两个功能硬件资源。 当以程序顺序连续并且在两个单独的功能硬件资源上执行的两个指令时，如果两个指令在硬件循环内，则两个指令的执行可以并行化。 因此，处理器可以通过与加法指令同时执行乘法指令（与乘法指令相比需要更少的周期来完成）来实现有效方式的乘法和累加过程。
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公开(公告)号：US07146613B2
公开(公告)日：2006-12-05
申请号：US10157530
申请日：2002-05-29
CPC分类号： G06F9/45504 , G06F8/4434
摘要： A digital system and method of operation is which the digital system has a processor with a virtual machine environment for interpretively executing instructions. First, a sequence of instructions is received (404) for execution by the virtual machine. The sequence of instructions is examined (408–414) to determine if a certain type of iterative sequence is present. If the certain type of iterative sequence is present, the iterative sequence is replaced (412) with a proprietary code sequence. After the modifications are complete, the modified sequence is executed in a manner that a portion of the sequence of instructions is executed in an interpretive manner (418); and the proprietary code sequences are executed directly by acceleration circuitry (420).
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公开(公告)号：US07120715B2
公开(公告)日：2006-10-10
申请号：US09932866
申请日：2001-08-17
IPC分类号： G06F13/14
CPC分类号： G06F12/1027 , G06F1/206 , G06F1/3203 , G06F1/329 , G06F9/30043 , G06F9/5094 , G06F9/52 , G06F12/0292 , G06F12/0879 , G06F12/0891 , G06F12/1081 , G06F2201/81 , G06F2201/885 , G06F2209/5014 , G06F2209/5021 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/24
摘要： A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. A memory management unit (MMU) (700) is connected to receive a request address (742) from each respective processor. The MMU has a set of entries that correspond to pages of address space. Each entry provides a set of attributes for the associated page of address space, including an address space priority value 309a. For each request, the MMU accesses an entry corresponding to the request address and provides an address space priority value associated with that requested address space page. Arbitration circuitry (1430) is connected to receive a request signal from each processor along with the access priority value from each access priority register and the address space priority value from each MMU. The arbitration circuitry is operable to schedule access to the shared resource according to higher of the pair of priority values provided by each processor.
摘要翻译： 提供了数字系统和操作方法，其中若干处理器（740（0）-704（n））连接到共享资源（750）。 每个处理器具有通过在处理器上执行的软件加载访问优先级值的访问优先级寄存器（1410）。 存储器管理单元（MMU）（700）被连接以从每个相应的处理器接收请求地址（742）。 MMU具有一组对应于地址空间页面的条目。 每个条目为相关联的地址空间页面提供一组属性，包括地址空间优先级值309a。 对于每个请求，MMU访问与请求地址相对应的条目，并提供与该请求的地址空间页相关联的地址空间优先级值。 连接仲裁电路（1430），从每个处理器接收来自每个访问优先级寄存器的访问优先级值和来自每个MMU的地址空间优先级值的请求信号。 仲裁电路可操作以根据由每个处理器提供的优先级对中的较高者调度对共享资源的访问。
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公开(公告)号：US20060026412A1
公开(公告)日：2006-02-02
申请号：US11186036
申请日：2005-07-21
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.
摘要翻译： 一种电子设备，包括包括单独指令和第一组指令的处理器。 该设备还包括外部耦合到处理器的存储器以及第二组指令。 当执行时，第一组指令使得处理器执行第二组指令来代替单独的指令。
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公开(公告)号：US20060026398A1
公开(公告)日：2006-02-02
申请号：US11116918
申请日：2005-04-28
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012 , Y02D10/13
摘要： A processor executes an instruction that causes a source data field from a programmable position within a first source register to be copied to a destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.
摘要翻译： 处理器执行使来自第一源寄存器中的可编程位置的源数据字段被复制到目的地寄存器的指令。 该指令对于生成基于媒体的比特流（例如，音频，视频）特别有用。 在一些实施例中，系统（例如，诸如蜂窝电话的通信设备）包括能够执行如上所述的指令的处理器。
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公开(公告)号：US20060026396A1
公开(公告)日：2006-02-02
申请号：US11116893
申请日：2005-04-28
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012 , Y02D10/13
摘要： A processor executes a load (or store) instruction that permits optional error checking to be performed. Based on a control bit in the load instruction, the processor executes the load instruction by causing contents of a source register to be compared to a predetermined value. If the contents of the source register equals the predetermined value, the processor executes an exception handler. However, if the source register contents differs from the predetermined value, the load instruction causes the processor to cause a data value from memory to be loaded into a destination register
摘要翻译： 处理器执行允许执行可选错误检查的加载（或存储）指令。 基于加载指令中的控制位，处理器通过使源寄存器的内容与预定值进行比较来执行加载指令。 如果源寄存器的内容等于预定值，则处理器执行异常处理程序。 然而，如果源寄存器内容与预定值不同，则加载指令使处理器将来自存储器的数据值加载到目的寄存器
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