公开(公告)号：US20220223688A1

公开(公告)日：2022-07-14

申请号：US17684498

申请日：2022-03-02

Applicant: GlobalFoundries U.S. INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L29/08 ,  H01L29/78

Abstract: The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.

公开(公告)号：US11378743B1

公开(公告)日：2022-07-05

申请号：US17146864

申请日：2021-01-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Roderick A. Augur ,  Kenneth J. Giewont ,  Karen Nummy ,  Edward Kiewra ,  Steven M. Shank

IPC: G02B6/122 ,  G02B6/34 ,  G02B6/136 ,  G02B6/12

Abstract: Structures including a grating coupler and methods of fabricating a structure including a grating coupler. The structure includes structure includes a dielectric layer on a substrate, a first waveguide core positioned in a first level over the dielectric layer, and a second waveguide core positioned in a second level over the dielectric layer. The second level differs in elevation above the dielectric layer from the first level. The first waveguide core includes a tapered section. The structure further includes a grating coupler having a plurality of segments positioned in the second level adjacent to the second waveguide core. The segments of the grating coupler and the tapered section of the first waveguide core are positioned in an overlapping arrangement.

公开(公告)号：US11374040B1

公开(公告)日：2022-06-28

申请号：US17113418

申请日：2020-12-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy ,  Ramsey Hazbun

IPC: H01L27/144 ,  H01L31/028 ,  H01L31/18 ,  H01L31/103 ,  H01L31/0312

Abstract: Structures including multiple photodiodes and methods of fabricating a structure including multiple photodiodes. A substrate has a first trench extending to a first depth into the substrate and a second trench extending to a second depth into the substrate that is greater than the first depth. A first photodiode includes a first light-absorbing layer containing a first material positioned in the first trench. A second photodiode includes a second light-absorbing layer containing a second material positioned in the second trench. The first material and the second material each include germanium.

公开(公告)号：US20220181501A1

公开(公告)日：2022-06-09

申请号：US17114554

申请日：2020-12-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Yves T. Ngu ,  Michael J. Zierak

IPC: H01L29/786 ,  H01L29/04 ,  H01L21/02 ,  H01L21/8234

Abstract: Disclosed is a structure including a semiconductor layer with a device area and, within the device area, a monocrystalline portion and polycrystalline portion(s) that extend through the monocrystalline portion. The structure includes an active device including a device component, which is in device area and which includes polycrystalline portion(s). For example, the device can be a field effect transistor (FET) (e.g., a simple FET or a multi-finger FET for a low noise amplifier or RF switch) with at least one source/drain region, which is in the device area and which includes at least one polycrystalline portion that extends through the monocrystalline portion. The embodiments can vary with regard to the type of structure (e.g., bulk or SOI), with regard to the type of device therein, and also with regard to the number, size, shape, location, orientation, etc. of the polycrystalline portion(s). Also disclosed is a method for forming the structure.

公开(公告)号：US11282883B2

公开(公告)日：2022-03-22

申请号：US16713423

申请日：2019-12-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Pekarik

IPC: H01L31/113 ,  H01L27/146

Abstract: Structures including a photodiode and methods of fabricating such structures. A trench extends from a top surface of a substrate to a depth into the substrate. The photodiode includes an active layer positioned in the trench. Trench isolation regions, which are located in the substrate, are arranged to surround the trench. A portion of the substrate is positioned in a surrounding relationship about the active layer and between the active layer and the trench isolation regions.

公开(公告)号：US11271079B2

公开(公告)日：2022-03-08

申请号：US16743584

申请日：2020-01-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L29/16 ,  H01L21/02 ,  H01L27/12 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a wafer with crystalline silicon and trap rich polysilicon layer and methods of manufacture. The structure includes: semiconductor-on-insulator (SOI) wafer composed of a lower crystalline semiconductor layer, a polysilicon layer over the lower crystalline semiconductor layer, an upper crystalline semiconductor layer over the polysilicon layer, a buried insulator layer over the upper crystalline semiconductor layer, and a top crystalline semiconductor layer over the buried insulator layer.

公开(公告)号：US11221506B2

公开(公告)日：2022-01-11

申请号：US16799100

申请日：2020-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02F1/01 ,  G02F1/035

Abstract: Structures for a polarization switch and methods of fabricating a structure for a polarization switch. A waveguide core is located on a substrate. The waveguide core is composed of silicon nitride. An active layer is positioned proximate to a section of the waveguide core. The active layer composed of a phase change material having a first state with a first refractive index and a second state with a second refractive index.

公开(公告)号：US11158535B2

公开(公告)日：2021-10-26

申请号：US16598064

申请日：2019-10-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Ian McCallum-Cook ,  Michel J. Abou-Khalil

IPC: H01L29/04 ,  H01L29/32 ,  H01L21/265 ,  H01L21/763 ,  H01L29/06 ,  H01L21/324 ,  H01L21/762 ,  H01L29/36 ,  H01L29/10

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. Shallow trench isolation regions extend from a top surface of a semiconductor substrate into the semiconductor substrate. The semiconductor substrate contains single-crystal semiconductor material, and the shallow trench isolation regions are positioned to surround an active device region of the semiconductor substrate. A polycrystalline layer is formed in the semiconductor substrate. The polycrystalline layer has a first section beneath the active device region and a second section beneath the plurality of shallow trench isolation regions. The first section of the polycrystalline layer is located at a different depth relative to the top surface of the semiconductor substrate than the second section of the polycrystalline layer.

公开(公告)号：US20210280672A1

公开(公告)日：2021-09-09

申请号：US16807453

申请日：2020-03-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  John J. Pekarik ,  Steven M. Shank ,  John J. Ellis-Monaghan

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/737 ,  H01L27/102 ,  H01L21/762

Abstract: Structures including electrical isolation and methods of forming a structure including electrical isolation. A semiconductor layer is formed over a semiconductor substrate and shallow trench isolation regions are formed in the semiconductor layer. The semiconductor layer includes single-crystal semiconductor material having an electrical resistivity that is greater than or equal to 1000 ohm-cm. The shallow trench isolation regions are arranged to surround a portion of the semiconductor layer to define an active device region. A polycrystalline layer is positioned in the semiconductor layer and extends laterally beneath the active device region and the shallow trench isolation regions that surround the active device region.

公开(公告)号：US11081561B2

公开(公告)日：2021-08-03

申请号：US16405469

申请日：2019-05-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Siva P. Adusumilli

IPC: H01L27/12 ,  H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/84 ,  H01L29/417

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. An isolation region is arranged to surround an active device region, which is composed of a semiconductor material. A trench is arranged in the active device region. The trench includes a bottom surface and a sidewall extending from the bottom surface to a top surface of the active device region. A gate electrode of the field-effect transistor has a first section on the top surface of the active device region, a second section on the bottom surface of the trench, and a third section on the sidewall of the trench.