公开(公告)号：US07809921B2

公开(公告)日：2010-10-05

申请号：US11930513

申请日：2007-10-31

申请人： Gordon Taylor Davis

发明人： Gordon Taylor Davis

IPC分类号： G06F12/00

CPC分类号： G06F12/1018 ,  G06F2212/1044

摘要： A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.

摘要翻译： 页表机制将虚拟地址转换为实地址。 在第一方面，页表条目包含在等大小的块中，每个块内的条目对应于虚拟地址空间的连续页面。 优选地，虚拟地址的公共高阶部分包含在分块在块的多个表表项之间的段中。 在第二方面，虚拟地址索引二进制树定义结构。 解码逻辑遍历由定义结构定义的二叉树，通过测试虚拟地址的选择性位以到达二叉树的叶，该二叉树定义了定义实际地址的数据的位置。

公开(公告)号：US07409520B2

公开(公告)日：2008-08-05

申请号：US11042692

申请日：2005-01-25

申请人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor Davis ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

发明人： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor Davis ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

IPC分类号： G06F12/00

CPC分类号： G06F9/3851 ,  G06F9/3802 ,  G06F9/4843

摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

摘要翻译： 公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。

公开(公告)号：US06947983B2

公开(公告)日：2005-09-20

申请号：US09887374

申请日：2001-06-22

申请人： Everett Arthur Corl, Jr. ,  Gordon Taylor Davis ,  Clark Debs Jeffries

发明人： Everett Arthur Corl, Jr. ,  Gordon Taylor Davis ,  Clark Debs Jeffries

IPC分类号： H04L29/06 ,  G06F15/173

CPC分类号： H04L63/0227 ,  H04L29/06 ,  H04L63/0263 ,  H04L69/22

摘要： A method and system for determining whether to enforce a plurality of filter rules for a packet including a key in a computer network is disclosed. Each of the plurality of filter rules has a priority. The method and system include accumulating statistics for each of the plurality of filter rules. The statistics indicate a frequency of enforcement for each of the plurality of filter rules. The method and system also include placing the plurality of filter rules in an order for testing against the key. The order is based on the frequency of each filter rule of the portion of the plurality of filter rules. Consequently, more frequently enforced filter rules may be tested first.

摘要翻译： 公开了一种用于确定是否对包括计算机网络中的密钥的分组执行多个滤波器规则的方法和系统。 多个过滤器规则中的每一个具有优先级。 该方法和系统包括累积多个过滤规则中的每一个的统计信息。 统计数据表示多个过滤规则中的每一个的执行频率。 该方法和系统还包括将多个过滤器规则放置成按照该键进行测试的顺序。 该顺序基于多个滤波器规则的该部分的每个滤波器规则的频率。 因此，可以首先测试更频繁地执行的过滤规则。

公开(公告)号：US06701447B1

公开(公告)日：2004-03-02

申请号：US09656547

申请日：2000-09-06

申请人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

发明人： Brian Mitchell Bass ,  Gordon Taylor Davis ,  Marco C. Heddes

IPC分类号： G06F104

CPC分类号： G06F11/3466 ,  G06F2201/86 ,  G06F2201/88

摘要： A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.

摘要翻译： 提供了用于执行延迟计数器增量的方法和结构。 该方法和结构允许基于计算机系统硬件对数据分组进行什么来修改计数器判定。 在产生计数器命令之后，数据分组的处理可能改变：例如，数据分组可以被丢弃而不是转发。 因此，计数器递增指令被改变。 延迟计数器增量将在数据包的处理完成后执行实际的计数器更新。 在本发明的一个实施例中，根据数据分组是转发还是丢弃，并且选择不同的计数器来更新计数器更新动作。 这解决了有时转发代码无法确定某些独立操作是否可能稍后丢弃数据包的问题。

公开(公告)号：US06141784A

公开(公告)日：2000-10-31

申请号：US979668

申请日：1997-11-26

申请人： Gordon Taylor Davis ,  Jeffrey Haskell Derby

发明人： Gordon Taylor Davis ,  Jeffrey Haskell Derby

IPC分类号： G08C25/02 ,  H04L1/00 ,  H04L1/16 ,  H04L1/18

CPC分类号： H04L1/1809 ,  G08C25/02 ,  H04L1/1628 ,  H04L2001/0092

摘要： A method and system in a data processing system are disclosed for the retransmission of only a portion of a data packet which had originally been transmitted incorrectly. A first data link is established between a first computer system and a second computer system. In response to the establishment of the first data link, a second data link is established between the first and second computer systems, whereby the first and second data links are related. A plurality of data packets are transmitted from the first computer system to the second computer system utilizing the first data link. Each of the data packets includes a plurality of segments. A determination is made whether each of the plurality of data packets is received correctly. In response to a determination that one of the plurality of data packets is received incorrectly, a portion of the data packet which was transmitted incorrectly is determined. Only the incorrectly transmitted portion of the data packet is then retransmitted by the first computer system utilizing the second data link.

摘要翻译： 公开了一种数据处理系统中的方法和系统，用于重传仅原始传输不正确的数据分组的一部分。 在第一计算机系统和第二计算机系统之间建立第一数据链路。 响应于建立第一数据链路，在第一和第二计算机系统之间建立第二数据链路，由此第一和第二数据链路是相关的。 利用第一数据链路将多个数据分组从第一计算机系统发送到第二计算机系统。 每个数据分组包括多个分段。 确定多个数据分组中的每一个是否被正确地接收。 响应于错误地接收到多个数据分组之一的确定，确定了发送不正确的数据分组的一部分。 然后，第一计算机系统仅利用第二数据链路重发数据分组的不正确发送的部分。

公开(公告)号：US6049902A

公开(公告)日：2000-04-11

申请号：US979044

申请日：1997-11-26

申请人： Gordon Taylor Davis ,  Jeffrey Haskell Derby

发明人： Gordon Taylor Davis ,  Jeffrey Haskell Derby

IPC分类号： H04L1/00 ,  H04L1/18 ,  G08C25/02 ,  H03M13/00

CPC分类号： H04L1/1809 ,  H04L2001/0096

摘要： A method and system in a data communications system are disclosed for the establishment of multiple, related data links and the utilization of one of the data links for error correction of transmission errors occurring on the other data link. A first data link is established between a first computer system and a second computer system. In response to the establishment of the first data link, a second, related data link is established between the first and second computer systems. A plurality of data packets are transmitted from the first computer system to the second computer system utilizing the first data link. A determination is made whether each of the plurality of data packets is received correctly. In response to each determination that one of the plurality of data packets is not received correctly, the second computer system transmits a selective rejection packet for the one of the plurality of data packets to the first computer system utilizing the second data link.

摘要翻译： 公开了一种数据通信系统中的方法和系统，用于建立多个相关数据链路，以及利用其中一个数据链路来纠错其他数据链路上发生的传输错误。 在第一计算机系统和第二计算机系统之间建立第一数据链路。 响应于建立第一数据链路，在第一和第二计算机系统之间建立第二相关数据链路。 利用第一数据链路将多个数据分组从第一计算机系统发送到第二计算机系统。 确定多个数据分组中的每一个是否被正确地接收。 响应于所述多个数据分组之一未被正确接收的每个确定，所述第二计算机系统利用所述第二数据链路向所述第一计算机系统发送所述多个数据分组中的所述一个数据分组的选择性拒绝分组。

公开(公告)号：US5859984A

公开(公告)日：1999-01-12

申请号：US695279

申请日：1996-08-06

申请人： Dana Lynn Blair ,  Gordon Taylor Davis ,  Cloyd Stanley McIlvaine

发明人： Dana Lynn Blair ,  Gordon Taylor Davis ,  Cloyd Stanley McIlvaine

IPC分类号： H04L29/06 ,  H04L29/08 ,  H04Q11/04 ,  H04L27/02

CPC分类号： H04Q11/0457 ,  H04L29/06 ,  H04L69/08 ,  H04L69/324 ,  H04Q2213/13093 ,  H04Q2213/13103 ,  H04Q2213/13199 ,  H04Q2213/13202 ,  H04Q2213/13204 ,  H04Q2213/13209 ,  H04Q2213/13216 ,  H04Q2213/13361 ,  H04Q2213/13362

摘要： Communication, using a synchronous protocol, over a synchronous communications link, between synchronous application programs executed on a terminal (i.e., personal computer, PC) with an asynchronous byte-oriented interface and a PC with a synchronous frame orientated interface is made possible by enhancing the PC with the asynchronous byte-oriented interface with a device which modifies the data to be transmitted by inserting framing flags and transparency characters before the data passes through the COMM port (asynchronous byte-oriented interface) and extracting the transparency characters after the data exits the COMM port. As a consequence, the PC with the frame-oriented interface does not have to be modified.

公开(公告)号：US5771232A

公开(公告)日：1998-06-23

申请号：US518215

申请日：1995-08-23

申请人： John Claude Sinibaldi ,  Baiju Dhirajlal Mandalia ,  Gordon Taylor Davis ,  Lawrence Paul Andrews ,  Robert Eugene Landa ,  Joe Fletcher Jones, Jr. ,  Willie James Johnson

发明人： John Claude Sinibaldi ,  Baiju Dhirajlal Mandalia ,  Gordon Taylor Davis ,  Lawrence Paul Andrews ,  Robert Eugene Landa ,  Joe Fletcher Jones, Jr. ,  Willie James Johnson

IPC分类号： G06F13/00 ,  H04J3/12 ,  H04J3/16 ,  H04L29/06 ,  H04L12/02

CPC分类号： H04L29/06 ,  H04J3/12 ,  H04J3/1641

摘要： In an communication system including a computer system comprising a digital signal processing adapter for performing a-set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.

摘要翻译： 在包括计算机系统的通信系统中，包括用于执行一组任务的数字信号处理适配器和根据第一系统间通信协议提供和接收时分多路复用（TDM）信号的E-1端口， 例如E-1或T-1协议，用于耦合到IP系统的通信子系统。 通信子系统包括用于耦合到第一I / O端口的E-1链路，以及用于根据E-1或T-1协议提供和接收TDM信号。 子系统还包括耦合到第二I / O端口的数字信号处理器适配器，用于增强数字信号处理资源的处理能力; 以及耦合到所述数字信号处理器电路的第三I / O端口，用于根据所述第一或第二系统间通信协议提供和接收信号。

公开(公告)号：US08200905B2

公开(公告)日：2012-06-12

申请号：US12192072

申请日：2008-08-14

申请人： Gordon Bernard Bell ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Anil Krishna ,  Srinivasan Ramani ,  Ken Vu ,  Steve Woolet

发明人： Gordon Bernard Bell ,  Gordon Taylor Davis ,  Jeffrey Haskell Derby ,  Anil Krishna ,  Srinivasan Ramani ,  Ken Vu ,  Steve Woolet

IPC分类号： G06F13/00

CPC分类号： G06F12/0862 ,  G06F12/0831 ,  G06F2212/6026

摘要： A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.

摘要翻译： 处理系统包括被配置为处理应用的存储器和第一核心。 第一个核心包括第一个缓存。 处理系统包括被配置为捕获错过第一核心中的第一高速缓存的应用程序的地址序列并将地址序列放置在存储阵列中的机制; 以及被配置为处理至少一个软件算法的第二核心。 所述至少一个软件算法利用来自存储阵列的地址序列来生成预取地址序列。 第二个核心将预取地址序列的预取请求发送到存储器以获得预取数据，并且如果请求，则将预取数据提供给第一核。

公开(公告)号：US08130650B2

公开(公告)日：2012-03-06

申请号：US12174999

申请日：2008-07-17

申请人： James Johnson Allen, Jr. ,  Brian Mitchell Bass ,  Gordon Taylor Davis ,  Clark Debs Jeffries ,  Jitesh Ramachandran Nair ,  Ravinder Kumar Sabhikhi ,  Michael Steven Siegel ,  Rama Mohan Yedavalli

发明人： James Johnson Allen, Jr. ,  Brian Mitchell Bass ,  Gordon Taylor Davis ,  Clark Debs Jeffries ,  Jitesh Ramachandran Nair ,  Ravinder Kumar Sabhikhi ,  Michael Steven Siegel ,  Rama Mohan Yedavalli

IPC分类号： H04L12/26

CPC分类号： H04L47/32 ,  H04L47/12 ,  H04L47/24 ,  H04L47/30 ,  H04L49/90

摘要： The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by storage and flow rate limits. The update includes comparing current queue occupancy to a threshold. The outcome of the update is adjustment up or down of the transmit probability value. The value is stored for the subsequent period of flow control and packets arriving during that period are subject to a transmit or discard decision that uses that value.

摘要翻译： 通过流控制方法和系统，在分组处理设备内决定将新到达的分组发送到队列中等待进一步处理或丢弃相同的分组。 流量控制以由存储和流量限制确定的恒定周期进行更新。 该更新包括将当前队列占用率与阈值进行比较。 更新的结果是传输概率值的上调或下调。 该值存储在随后的流量控制周期中，并且在该时间段期间到达的分组经受使用该值的发送或丢弃决定。