公开(公告)号：US20130262778A1

公开(公告)日：2013-10-03

申请号：US13433048

申请日：2012-03-28

申请人： Sanjeev Ghai ,  Guy L. Guthrie ,  William J. Starke ,  Jeff A. Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

发明人： Sanjeev Ghai ,  Guy L. Guthrie ,  William J. Starke ,  Jeff A. Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/12

CPC分类号： G06F12/0817 ,  G06F12/0804 ,  G06F12/121 ,  G06F12/122 ,  G06F12/126

摘要： In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.

摘要翻译： 响应于执行取消分配指令，将指定目标高速缓存行的目标地址的解除分配请求从处理器核发送到较低级高速缓存。 作为响应，确定目标地址是否在较低级别高速缓存中。 如果是这样，则目标高速缓存行被保留在较低级高速缓存的数据阵列中，并且更新较低级高速缓存的替换顺序字段，使得目标高速缓存行更可能响应于后续高速缓存未命中而被驱逐 在包含目标缓存行的同余类中。 响应于随后的高速缓存未命中，目标高速缓存行被推出到较低级缓存，指示目标高速缓存行是处理器核心的先前释放请求的目标。

公开(公告)号：US08510512B2

公开(公告)日：2013-08-13

申请号：US12545246

申请日：2009-08-21

申请人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

发明人： Paul A. Ganfield ,  Guy L. Guthrie ,  David J. Krolak ,  Michael S. Siegel ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F12/0817

摘要： A data processing system includes at least a first through third processing nodes coupled by an interconnect fabric. The first processing node includes a master, a plurality of snoopers capable of participating in interconnect operations, and a node interface that receives a request of the master and transmits the request of the master to the second processing unit with a nodal scope of transmission limited to the second processing node. The second processing node includes a node interface having a directory. The node interface of the second processing node permits the request to proceed with the nodal scope of transmission if the directory does not indicate that a target memory block of the request is cached other than in the second processing node and prevents the request from succeeding if the directory indicates that the target memory block of the request is cached other than in the second processing node.

公开(公告)号：US08332588B2

公开(公告)日：2012-12-11

申请号：US13349315

申请日：2012-01-12

申请人： Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/04

CPC分类号： G06F12/0822

摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.

摘要翻译： 分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由 存储修改结构随后由所述预处理代码引用。 生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。 生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒 将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。

公开(公告)号：US20120265938A1

公开(公告)日：2012-10-18

申请号：US13349315

申请日：2012-01-12

申请人： Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0822

摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.

摘要翻译： 分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由 存储修改结构随后由所述预处理代码引用。 生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。 生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒 将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。

公开(公告)号：US20120210072A1

公开(公告)日：2012-08-16

申请号：US13456420

申请日：2012-04-26

申请人： Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0837 ,  G06F12/0895

摘要： A method of processing store requests in a data processing system includes enqueuing a store request in a store queue of a cache memory of the data processing system. The store request identifies a target memory block by a target address and specifies store data. While the store request and a barrier request older than the store request are enqueued in the store queue, a read-claim machine of the cache memory is dispatched to acquire coherence ownership of target memory block of the store request. After coherence ownership of the target memory block is acquired and the barrier request has been retired from the store queue, a cache array of the cache memory is updated with the store data.

摘要翻译： 在数据处理系统中处理存储请求的方法包括在数据处理系统的高速缓存存储器的存储队列中引入存储请求。 存储请求通过目标地址识别目标存储器块并指定存储数据。 当存储请求和存储请求之前的屏障请求在存储队列中排队时，调度高速缓冲存储器的读取机器以获取存储请求的目标存储器块的一致性所有权。 在获取目标存储器块的一致性所有权并且屏障请求已经从存储队列中退出之后，用存储数据更新高速缓冲存储器的高速缓存阵列。

公开(公告)号：US08225045B2

公开(公告)日：2012-07-17

申请号：US12335975

申请日：2008-12-16

申请人： Guy L. Guthrie ,  Alvan W. Ng ,  Michael S. Siegel ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

发明人： Guy L. Guthrie ,  Alvan W. Ng ,  Michael S. Siegel ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0862

摘要： A data processing system includes a first processing unit and a second processing unit coupled by an interconnect fabric. The first processing unit has a first processor core and associated first upper and first lower level caches, and the second processing unit has a second processor core and associated second upper and lower level caches. In response to a data request, a victim cache line is selected for castout from the first lower level cache. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that a lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.

摘要翻译： 数据处理系统包括由互连结构耦合的第一处理单元和第二处理单元。 第一处理单元具有第一处理器核心和相关联的第一上部和第一下层高速缓存，并且第二处理单元具有第二处理器核心和相关联的第二上部和下部高速缓存。 响应于数据请求，选择受害者高速缓存行用于从第一较低级别缓存进行舍弃。 第一处理单元在互连结构上发出横向聚合（LCO）命令，该命令标识要从第一较低级缓存中抛出的受害缓存行，并且指示较低级缓存是预期目的地。 响应于指示LCO命令的成功的一致性响应，从第一低级缓存中删除受害者高速缓存行并保存在第二较低级高速缓存中。

公开(公告)号：US08117390B2

公开(公告)日：2012-02-14

申请号：US12424434

申请日：2009-04-15

申请人： David W. Cummings ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

发明人： David W. Cummings ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F13/00

CPC分类号： G06F12/0822 ,  G06F12/0897 ,  G06F2212/507

摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.

摘要翻译： 用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。 处理单元还包括耦合到并支持处理器核的多级高速缓存层级。 多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。 响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送至至少一个上级高速缓冲存储器来服务存储器访问请求。 至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

公开(公告)号：US20110161589A1

公开(公告)日：2011-06-30

申请号：US12650018

申请日：2009-12-30

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey A. Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/12

摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

摘要翻译： 数据处理系统包括第一和第二处理单元和系统存储器。 第一处理单元具有第一上层和第一下层高速缓存，第二处理单元具有第二上层和下层高速缓存。 响应于数据请求，选择要从第一较低级高速缓存丢弃的受害者高速缓存行，并且第一较低级高速缓存选择在执行到第二低级高速缓存的受害者高速缓存行的横向流出（LCO） 基于与受害者高速缓存行相关联的置信指示，将受害者缓存行的丢弃发送到系统存储器。 响应于选择LCO，第一处理单元在互连结构上发布LCO命令，并从第一低级缓存中移除受害者高速缓存行，并且第二下级缓存保存受害缓存行。

公开(公告)号：US07941611B2

公开(公告)日：2011-05-10

申请号：US12106102

申请日：2008-04-18

申请人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

发明人： Benjiman L. Goodman ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least a first cache memory supporting a first processing unit and a second cache memory supporting a second processing unit. The first cache memory includes a cache array and a cache directory of contents of the cache array. In response to the first cache memory detecting on an interconnect a broadcast operation that specifies a request address, the first cache memory determines from the operation a type of the operation and a coherency state associated with the request address. In response to determining the type and the coherency state, the first cache memory filters out the broadcast operation without accessing the cache directory.

摘要翻译： 高速缓存一致数据处理系统至少包括支持第一处理单元的第一高速缓冲存储器和支持第二处理单元的第二高速缓冲存储器。 第一缓存存储器包括缓存阵列和高速缓存阵列的内容的高速缓存目录。 响应于第一高速缓冲存储器在互连上检测指定请求地址的广播操作，第一高速缓冲存储器从操作中确定与请求地址相关联的操作类型和一致性状态。 响应于确定类型和一致性状态，第一高速缓存存储器过滤掉广播操作而不访问高速缓存目录。

公开(公告)号：US07543116B2

公开(公告)日：2009-06-02

申请号：US11342951

申请日：2006-01-30

申请人： Guy L. Guthrie ,  John T. Hollaway, Jr. ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  John T. Hollaway, Jr. ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0822 ,  G06F12/0804 ,  G06F12/0831

摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target memory block identified by a target address, and a domain indicator indicating whether the target memory block is cached outside the first coherency domain. During operation, the first coherency domain receives a flush operation broadcast to the first and second coherency domains, where the flush operation specifies the target address of the target memory block. The first coherency domain also receives a combined response for the flush operation representing a system-wide response to the flush operation. In response to receipt in the first coherency domain of the combined response, a determination is made if the combined response indicates that a cached copy of the target memory block may remain within the data processing system. In response to a determination that the combined response indicates that a cached copy of the target memory block may remain in the data processing system, the domain indicator is updated to indicate that the target memory block is cached outside of the first coherency domain.

摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 第一相干域包括存储器控制器，具有由目标地址标识的目标存储器块的相关系统存储器，以及指示目标存储器块是否被高速缓存在第一相干域之外的域指示符。 在操作期间，第一相干域接收向第一和第二相干域广播的刷新操作，其中刷新操作指定目标存储器块的目标地址。 第一个相干域还接收表示对刷新操作的系统范围响应的刷新操作的组合响应。 响应于在组合响应的第一相关域中的接收，确定组合响应是否指示目标存储器块的高速缓存副本可能保留在数据处理系统内。 响应于确定组合响应指示目标存储器块的高速缓存副本可能保留在数据处理系统中，则域指示符被更新以指示目标存储器块被高速缓存在第一相干域之外。