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公开(公告)号：US08471595B1
公开(公告)日：2013-06-25
申请号：US13353383
申请日：2012-01-19
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K3/35606 , G06F7/68 , H03K19/1737
摘要： A selectable latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. The output of the parallel pass gates and the additional pass gate is connected to a feedback loop. The feedback loop operates as a dynamic latch for high frequency applications or as a static latch for low frequency applications. Thus, the selectable latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal.
摘要翻译： 可选择的锁存器具有一对并行通过门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。 第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。 附加的通过门可操作地连接到第一锁存逻辑电路。 一个附加的传递门控制更新的数据信号的通过。 并联栅极和附加栅极的输出端连接到反馈回路。 反馈回路作为高频应用的动态锁存器或作为低频应用的静态锁存器。 因此，可选择的锁存器包括两个输入到该对并行通道门中，并且仅对接收的数据信号执行四个逻辑运算中的一个。
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公开(公告)号：US08381052B2
公开(公告)日：2013-02-19
申请号：US12615856
申请日：2009-11-10
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/76 , G11C2029/0401
摘要： A circuit and method of testing a memory and calculating a repair solution for a given address location includes pausing a built in self test (BIST) operation on detection of a failing memory output data of an integrated circuit. During the pause, the circuit and method analyzes “n” number of groups of the failing memory output data during “n” cycles using analysis logic and calculating a repair solution. Normal operations can be resumed.
摘要翻译： 一种用于测试存储器并为给定地址位置计算修复解决方案的电路和方法包括：在检测集成电路的故障存储器输出数据时暂停内置自检（BIST）操作。 在暂停期间，电路和方法在n个周期内使用分析逻辑分析n个故障存储器输出数据组，并计算修复解决方案。 正常操作可以恢复。
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公开(公告)号：US08239818B1
公开(公告)日：2012-08-07
申请号：US13080055
申请日：2011-04-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14 , G11C29/12
摘要： A system and associated data structure that can be utilized within a chip design platform to define the structure of an MBIST architecture. A system for generating a memory built in self test (MBIST) design file in described, including a tool for processing an organization file (Org File), wherein the Org File includes lines of code that dictate a structure of the MBIST design file and conform to a data structure defined by the tool; wherein said data structure provides an infrastructure to describe: associations between MBIST components at a design level; associations between MBIST components and hierarchical test ports at the design level; and a serial order of daisy chains among MBIST components within the design level.
摘要翻译： 可以在芯片设计平台内使用的系统和相关数据结构来定义MBIST架构的结构。 一种用于生成内置于自我测试（MBIST）设计文件中的内存的系统，包括用于处理组织文件（Org File）的工具，其中组织文件包括指定MBIST设计文件的结构并符合的代码行 到工具定义的数据结构; 其中所述数据结构提供基础设施以描述：在设计级别的MBIST组件之间的关联; MBIST组件与分级测试端口在设计级别之间的关联; 以及在设计级别的MBIST组件之间的菊花链的串行顺序。
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公开(公告)号：US20120176144A1
公开(公告)日：2012-07-12
申请号：US12986546
申请日：2011-01-07
申请人： Vikram Iyengar , Animesh Khare , Michael R. Ouellette , Narendra K. Rane , Umesh K. Shukla , Pradeep K. Vanama
发明人： Vikram Iyengar , Animesh Khare , Michael R. Ouellette , Narendra K. Rane , Umesh K. Shukla , Pradeep K. Vanama
CPC分类号： G01R31/318572 , G01R31/318541
摘要： A circuit for providing a local scan enable signal includes a first transistor having a first gate coupled to a general scan enable signal, a first source and a first drain and a second transistor having a second gate coupled to a scan clock, a second source coupled to the first drain and a second drain. The circuit also includes a third transistor having a third gate coupled to the general scan enable signal, a third drain coupled to the second drain and a third source and an output stabilizer coupled to the second drain, the output stabilizer including a first inverter and a second inverter coupled together in opposite orientations.
摘要翻译： 用于提供本地扫描使能信号的电路包括具有耦合到一般扫描使能信号的第一栅极的第一晶体管，第一源极和第一漏极以及耦合到扫描时钟的第二栅极的第二晶体管， 到第一排水口和第二排水管。 电路还包括第三晶体管，其具有耦合到通用扫描使能信号的第三栅极，耦合到第二漏极的第三漏极和耦合到第二漏极的第三源极和输出稳定器，输出稳定器包括第一反相器和 第二个逆变器以相反的方向耦合在一起。
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65.发明授权Structure for system for and method of performing high speed memory diagnostics via built-in-self-test 失效用于通过内置自检进行高速存储器诊断的系统和方法的结构公开(公告)号：US07870454B2
公开(公告)日：2011-01-11
申请号：US12126452
申请日：2008-05-23
CPC分类号： G11C29/40 , G01R31/31703 , G01R31/31704 , G11C2029/3202
摘要： A design structure for a system for and method of performing high speed memory diagnostics via built-in-self-test (BIST) is disclosed. In particular, a test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method of performing high speed memory diagnostics via BIST includes, but is not limited to, presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm and performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译： 公开了一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法的设计结构。 特别地，测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。 测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。 通过BIST执行高速存储器诊断的方法包括但不限于预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑的等待时间的值，设置BIST周期计数器 将可变延迟预置为零，重新执行测试算法并执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。
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66.发明授权Automatically extensible addressing for shared array built-in self-test (ABIST) circuitry 有权用于共享阵列内置自检（ABIST）电路的自动扩展寻址公开(公告)号：US07757141B2
公开(公告)日：2010-07-13
申请号：US12055595
申请日：2008-03-26
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31722
摘要： A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.
摘要翻译： 一种用于通过自动扩展用于共享阵列内置自检（BIST）电路的寻址来测试集成电路（IC）的方法，包括轮询多个存储器以确定多个存储器中的哪个存储器共享第一比较树并映射 使用第一比较树将共享阵列BIST地址空间分配给多个存储器中的每一个。 另外，该方法包括估计对应于被测试的最大总存储器地址大小的最高有效位的共享阵列BIST完成时间，重新配置共享阵列BIST电路以适应估计的共享阵列BIST完成时间并测试多个存储器共享 第一个比较树。
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67.发明申请METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK 有权设计多状态恢复电路以将状态恢复到功率管理的功能块的方法公开(公告)号：US20090307637A1
公开(公告)日：2009-12-10
申请号：US12135250
申请日：2008-06-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/72
摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.
摘要翻译： 设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。 在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。 由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。 恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。 如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。
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68.发明授权System and method for performing high speed memory diagnostics via built-in-self-test 有权通过内置自检进行高速存储器诊断的系统和方法公开(公告)号：US07607060B2
公开(公告)日：2009-10-20
申请号：US11531035
申请日：2006-09-12
CPC分类号： G11C29/44 , G11C2029/3202
摘要： A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method includes presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm, performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译： 一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法。 测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。 测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。 一种方法包括预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑等待时间的值，将BIST周期计数器设置为递减模式，将可变延迟预置为零，重新执行 测试算法，执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。
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公开(公告)号：US20090251169A1
公开(公告)日：2009-10-08
申请号：US12099382
申请日：2008-04-08
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： H03K19/018585 , H03K19/018557 , H03K19/018592
摘要： A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality.
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70.发明申请Programmable Locking Mechanism For Secure Applications In An Integrated Circuit 审中-公开可编程锁定机制，用于集成电路中的安全应用公开(公告)号：US20080155151A1
公开(公告)日：2008-06-26
申请号：US11615137
申请日：2006-12-22
IPC分类号： G06F21/00
CPC分类号： G06K19/073 , G06K19/07309
摘要： A programmable locking mechanism for use in an integrated circuit is disclosed. In particular, the programmable locking mechanism may include an access code storage circuit for storing a security access code and a code input register whose outputs feed a comparator circuit that generates a locking signal. The state of the locking signal depends on whether the contents of the access code storage circuit and the code input register match. Additionally, a blocking circuit is provided that interrupts a programming input to the access code storage circuit and, thus, allows or denies access via the programming input to the access code storage circuit depending on the state of the locking signal. Additionally, the locking signal is distributed to sensitive logic circuits within the integrated circuit for preventing and/or allowing (depending on state) access thereto.
摘要翻译： 公开了一种用于集成电路的可编程锁定机构。 特别地，可编程锁定机构可以包括用于存储安全访问代码的访问代码存储电路和其输出馈送产生锁定信号的比较器电路的代码输入寄存器。 锁定信号的状态取决于访问代码存储电路和代码输入寄存器的内容是否匹配。 此外，提供一种阻塞电路，其中断对访问代码存储电路的编程输入，并且因此根据锁定信号的状态允许或拒绝通过对访问代码存储电路的编程输入的访问。 此外，锁定信号被分配到集成电路内的敏感逻辑电路，用于防止和/或允许（取决于状态）对其的访问。
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