公开(公告)号：US07917560B2

公开(公告)日：2011-03-29

申请号：US11635590

申请日：2006-12-08

申请人： Mari Matsumoto ,  Tetsufumi Tanamoto ,  Shinobu Fujita

发明人： Mari Matsumoto ,  Tetsufumi Tanamoto ,  Shinobu Fujita

IPC分类号： G06F1/02

CPC分类号： G06F7/58 ,  G06F17/15

摘要： The random number test circuit includes a shift register which operates based on a clock and which successively stores serial random numbers generated by a random number generation element, a first random number being output from a predetermined stage of the shift register; a comparison circuit which compares the first random number with a second random number located at a distance of a first predetermined number of bits from the first random number, the second random number being generated by the random number generation element; a counter which counts a frequency of occurrence of equality or inequality between the first random number and the second random number, with respect to all bits in the serial random numbers, and a decision circuit which judges an article quality to be good if a count value in the counter indicates a frequency of occurrence equal to or less than a number determined previously by correlation.

摘要翻译： 该随机数测试电路包括一个移位寄存器，该移位寄存器基于时钟进行操作，并连续地存储由随机数生成元件生成的串行随机数，第一随机数从移位寄存器的预定级输出; 比较电路，其将所述第一随机数与位于距所述第一随机数的第一预定位数的距离的第二随机数进行比较，所述第二随机数由所述随机数生成元生成; 相对于串行随机数中的所有比特来计算第一随机数和第二随机数之间的相等或不等式的发生频率的计数器，以及判断电路，如果计数值 在计数器中表示发生的频率等于或小于先前通过相关性确定的数字。

公开(公告)号：US07558813B2

公开(公告)日：2009-07-07

申请号：US12143104

申请日：2008-06-20

申请人： Tetsufumi Tanamoto ,  Shinobu Fujita

发明人： Tetsufumi Tanamoto ,  Shinobu Fujita

IPC分类号： G06F7/58 ,  H01L29/772

CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

公开(公告)号：US20080211540A1

公开(公告)日：2008-09-04

申请号：US12038807

申请日：2008-02-27

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： H03K19/173

CPC分类号： H03K19/17748 ,  H03K19/1776 ,  H03K19/1778

摘要： According to some embodiments, an “excess-current programming method” on ZnCdS memory devices for FPGA applications is disclosed. an “excess-current programming method” can also be employed within a variety of other applications, including other memory devices having low On-resistance, such as, e.g., metal-oxide memory like Ti-oxide, Ni-oxide, W-oxide, Cu-oxide and so on. Embodiments of ZnCdS based devices (e.g., memory devices), FPGA elements incorporating the same and methods thereof for reconfigurable circuits can reduce area overhead, power overhead and/or latency (e.g., of FPGA), address a disturbance problem during logic operation, decrease an ON-resistance characteristic and/or obtain increased data retention.

摘要翻译： 根据一些实施例，公开了用于FPGA应用的ZnCdS存储器件上的“过电流编程方法”。 也可以在各种其他应用中使用“过电流编程方法”，包括具有低导通电阻的其它存储器件，例如诸如氧化钛，氧化镍，氧化钼的金属氧化物存储器 ，氧化铜等。 基于ZnCdS的器件（例如，存储器件），与其组合的FPGA元件及其可重构电路的方法的实施例可以减少面积开销，功率开销和/或等待时间（例如FPGA），解决逻辑运算期间的干扰问题，减少 导通电阻特性和/或获得增加的数据保留。

公开(公告)号：US20070296025A1

公开(公告)日：2007-12-27

申请号：US11743265

申请日：2007-05-02

申请人： Mari Matsumoto ,  Ryuji Ohba ,  Shinobu Fujita

发明人： Mari Matsumoto ,  Ryuji Ohba ,  Shinobu Fujita

IPC分类号： H01L29/792

CPC分类号： G06F7/588 ,  H03B29/00

摘要： A random number generating device includes a semiconductor device including a source region, a drain region, a channel region provided between the source region and the drain region, and an insulating portion provided on the channel region, the insulating portion including a trap insulating film having traps based on dangling bonds and expressed by Six(SiO2)y(Si3N4)1-yMz (M is an element other than Si, O, and N, x≧0, 1≧y≧0, z≧0, the case where x=0 and y=1 and z=0 is excluded), conductivity of the channel region varying randomly depending on the amount of charge caught in the traps, and a random number generating unit connected to the semiconductor device and generating random numbers based on a random variation in the conductivity of the channel region.

摘要翻译： 随机数发生装置包括：半导体器件，包括源区域，漏极区域，设置在源极区域和漏极区域之间的沟道区域;以及绝缘部分，设置在沟道区域上，绝缘部分包括捕获绝缘膜， 基于悬挂键并由Si x Si（SiO 2）y（Si 3 N）3表示的陷阱 （M是除Si，O和N之外的元素，x> = 0,1，= y> = 0，z> = 0，x = 0且y = 1，z = 0的情况除外），根据陷阱中捕获的电荷量随机地变化的信道区域的导电率和连接的随机数发生单元 并且基于沟道区域的导电性的随机变化产生随机数。

公开(公告)号：US07111029B2

公开(公告)日：2006-09-19

申请号：US10235827

申请日：2002-09-06

申请人： Shinobu Fujita ,  Ken Uchida ,  Ryuji Ohba ,  Junji Koga

发明人： Shinobu Fujita ,  Ken Uchida ,  Ryuji Ohba ,  Junji Koga

IPC分类号： G06F1/02

CPC分类号： H04L9/0861 ,  G06F7/588

摘要： A random number generating circuit can generate random numbers with high randomness, and can be made as a compact integrated circuit. The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance frequencies of “0” and “1” in the digital output values output from the uncertain logic circuit.

公开(公告)号：US07001787B2

公开(公告)日：2006-02-21

申请号：US10902301

申请日：2004-07-30

申请人： Tetsufumi Tanamoto ,  Satoshi Saito ,  Shinobu Fujita

发明人： Tetsufumi Tanamoto ,  Satoshi Saito ,  Shinobu Fujita

IPC分类号： H01L21/00

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  G11C13/025 ,  H01J9/025 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  Y10T428/256 ,  Y10T428/259

摘要： An electrode manufacturing method comprises: forming plural protruding portions on a surface of a substrate; introducing first particles having a size that changes according to heat, light, or a first solvent between said plural protruding portions; changing the size of the first particles by applying heat, light, or the first solvent to said first particles; and depositing an electrode material onto the surface of said substrate.

摘要翻译： 电极制造方法包括：在基板的表面上形成多个突出部分; 在所述多个突出部之间引入具有根据热，光或第一溶剂变化的尺寸的第一颗粒; 通过向所述第一颗粒施加热，光或第一溶剂来改变第一颗粒的尺寸; 以及将电极材料沉积到所述衬底的表面上。

公开(公告)号：US08716805B2

公开(公告)日：2014-05-06

申请号：US12237152

申请日：2008-09-24

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： H01L27/00

CPC分类号： H01L27/0688 ,  H01L27/101

摘要： A complementary metal oxide semiconductor (CMOS) circuit having integrated functional devices such as nanowires, carbon nanotubes, magnetic memory cells, phase change memory cells, ferroelectric memory cells or the like. The functional devices are integrated with the CMOS circuit. The functional devices are bonded (e.g. by direct bonding, anodic bonding, or diffusion bonding) to a top surface of the CMOS circuit. The functional devices are fabricated and processed on a carrier wafer, and an attachment layer (e.g. SiO2) is deposited over the functional devices. Then, the CMOS circuit and attachment layer are bonded. The carrier wafer is removed (e.g. by etching). The functional devices remain attached to the CMOS circuit via the attachment layer. Apertures are etched through the attachment layer to provide a path for electrical connections between the CMOS circuit and the functional devices.

摘要翻译： 具有纳米线，碳纳米管，磁存储单元，相变存储单元，铁电存储单元等集成功能元件的互补金属氧化物半导体（CMOS）电路。 功能器件与CMOS电路集成。 功能器件通过例如直接接合，阳极结合或扩散接合来结合到CMOS电路的顶表面。 功能器件在载体晶片上制造和处理，并且在功能器件上沉积附着层（例如SiO 2）。 然后，连接CMOS电路和附着层。 移除载体晶片（例如通过蚀刻）。 功能器件通过附着层保持连接到CMOS电路。 孔径通过附着层蚀刻，以提供用于CMOS电路和功能器件之间的电连接的路径。

公开(公告)号：US08611143B2

公开(公告)日：2013-12-17

申请号：US13403308

申请日：2012-02-23

申请人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

发明人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

IPC分类号： G11C11/00

CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

公开(公告)号：US08239809B2

公开(公告)日：2012-08-07

申请号：US12504272

申请日：2009-07-16

申请人： Shinobu Fujita

发明人： Shinobu Fujita

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： A 3-dimensional integrated circuit designing method includes forming a temporary layout region for an original integrated circuit on an XY plane, the plane being short in an X direction and long in a Y direction perpendicular to the X direction, dividing the temporary layout region into 2N (N is an integral number of not smaller than 2) or more subregions in the Y direction, configuring one block for every successive N subregions to prepare a plurality of blocks, and forming N layers of layout by alternately folding each of the blocks in the Y direction in units of one subregion to selectively set a kN-th (k is an integral number not less than 1) subregion and (kN+1)th subregion of each block to one of an uppermost layer and lowermost layer.

摘要翻译： 三维集成电路设计方法包括在XY平面上形成用于原始集成电路的临时布局区域，该平面在X方向上短并且在垂直于X方向的Y方向上长，将临时布局区域分成 2N（N是不小于2的整数）或更多个子区域，为每个连续的N个子区域配置一个块以准备多个块，并且通过交替地将每个块的每个块交替地折叠来形成N个层的布局 以一个子区域为单位的Y方向，选择性地将各块的kN（k为1以上的整数）子区域和（kN + 1）个子区域设置为最上层和最下层中的一个。

公开(公告)号：US08073889B2

公开(公告)日：2011-12-06

申请号：US12153410

申请日：2008-05-19

申请人： Shinobu Fujita ,  Tetsuro Iwamura

发明人： Shinobu Fujita ,  Tetsuro Iwamura

IPC分类号： G06F7/02

CPC分类号： G06F7/588 ,  H04L9/0869

摘要： A random number generating circuit comprises: the seed generating circuit which generates a seed; and a pseudo random number circuit which generates pseudo random numbers based on the seed generated by the seed generating circuit. The seed generating circuit has: an oscillating circuit which oscillates continuously or intermittently, and which outputs a digital data sequence; a smoothing circuit which outputs time series data by controlling appearance frequencies of “0” and “1” in the digital data sequence outputted from the oscillating circuit; and a postprocessing circuit which generates one-bit seed by a computation using a plurality of bits included in the time series data.

摘要翻译： 随机数生成电路包括：种子生成电路，其生成种子; 以及伪随机数电路，其基于种子生成电路生成的种子生成伪随机数。 种子生成电路具有：连续或间歇地振荡并且输出数字数据序列的振荡电路; 平滑电路，其通过控制从振荡电路输出的数字数据序列中的出现频率“0”和“1”输出时间序列数据; 以及后处理电路，其通过使用包括在时间序列数据中的多个位的计算来生成一位种子。