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    Method for implementing circuit design for integrated circuit and computer readable medium
    1.
    发明授权
    Method for implementing circuit design for integrated circuit and computer readable medium 失效
    集成电路和计算机可读介质电路设计实现方法

    公开(公告)号：US08578318B2

    公开(公告)日：2013-11-05

    申请号：US13561483

    申请日：2012-07-30

    申请人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

    发明人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5081

    摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.

    摘要翻译： 在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中 分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线 长度。

    Programmable logic switch
    2.
    发明授权
    Programmable logic switch 有权
    可编程逻辑开关

    公开(公告)号：US08432186B1

    公开(公告)日：2013-04-30

    申请号：US13484639

    申请日：2012-05-31

    申请人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Shinichi Yasuda ,  Masato Oda ,  Haruka Kusai ,  Kiwamu Sakuma

    发明人： Koichiro Zaitsu ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Shinichi Yasuda ,  Masato Oda ,  Haruka Kusai ,  Kiwamu Sakuma

    IPC分类号： H03K19/173

    CPC分类号： H03K19/018585 ,  G11C5/146 ,  G11C16/10 ,  G11C16/12 ,  H03K19/1737

    摘要： One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.

    摘要翻译： 一个实施例提供一种可编程逻辑开关，其中在同一个阱中形成第一非易失性存储器和第二非易失性存储器，并且其中将第一非易失性存储器从擦除状态改变为写入状态，并使第二非易失性存储器处于 擦除状态时，将第一写入电压施加到与第一和第二非易失性存储器的栅电极连接的第一线，第二写入电压被施加到连接到第一非易失性存储器中的源极的第二线，并且第三写入 低于第二写入电压的电压被施加到连接到第二非易失性存储器的源极的第四线路。

    Method and apparatus for charging high-viscous material
    5.
    发明授权
    Method and apparatus for charging high-viscous material 失效
    高粘度材料充电的方法和装置

    公开(公告)号：US5126084A

    公开(公告)日：1992-06-30

    申请号：US659087

    申请日：1991-02-22

    申请人： Hiromitu Ibe ,  Kenji Matumoto ,  Toshikatsu Nakashima ,  Masato Oda

    发明人： Hiromitu Ibe ,  Kenji Matumoto ,  Toshikatsu Nakashima ,  Masato Oda

    IPC分类号： B65B3/12 ,  B29B9/12 ,  B29B13/00 ,  B65B3/18

    CPC分类号： B29B9/12 ,  B29B13/00

    摘要： The present invention relates to a method and apparatus for charging a high-viscous material in a material tank into a charging tank. The high-viscous material, namely, putty is used preferably as a material for correcting the dynamic unbalance of a rotary body. When the material is charged from the material tank into the charging tank through a nozzle, the pressure of air in the charging tank is reduced and the pressure of air in the material tank is increased to drop the high-viscous material in droplets without taking air thereinto and air which has permeated into the material in the material tank can be removed.

    摘要翻译： 本发明涉及一种用于将材料罐中的高粘度材料装入充电罐的方法和装置。 高粘度材料，即油灰，优选用作用于校正旋转体的动态不平衡的材料。 当通过喷嘴将材料从材料罐装入充电槽时，充电槽中的空气压力降低，并且材料罐中的空气压力增加，以使高粘度材料滴落而不吸入空气 并且可以除去渗透到料箱中的材料中的空气。

    Look-up table circuit
    6.
    发明授权
    Look-up table circuit 有权
    查询表电路

    公开(公告)号：US08970249B2

    公开(公告)日：2015-03-03

    申请号：US13606041

    申请日：2012-09-07

    申请人： Masato Oda ,  Shinichi Yasuda

    发明人： Masato Oda ,  Shinichi Yasuda

    IPC分类号： H03K19/173

    CPC分类号： G11C5/148

    摘要： One embodiment provides a look-up table circuit, including: 2i memories, a half of which constituting a first memory group, the other half of which constituting a second memory group; first to i-th input terminals to which first to i-th input signals are input, respectively; a first output terminal; a switch group that selectively connects one of the memories to the first output terminal according to the first to i-th input signals; a first power-off switch that shuts off power supply to the first memory group in response to one of the first to i-th input signals; and a second power-off switch that shuts off power supply to the second memory group in response to the one of the first to i-th input signals.

    摘要翻译： 一个实施例提供了一种查找表电路，包括：2i个存储器，其中一半构成第一存储器组，另一半构成第二存储器组; 分别输入第一至第i输入信号的第一至第i输入端子; 第一输出端子; 开关组，根据第一至第i输入信号有选择地将一个存储器连接到第一输出端; 第一断电开关，其响应于第一至第i输入信号中的一个切断对第一存储器组的电源; 以及第二断电开关，其响应于所述第一至第i输入信号之一而切断对所述第二存储器组的电源。

    MEMORY CIRCUIT AND FIELD PROGRAMMABLE GATE ARRAY
    7.
    发明申请
    MEMORY CIRCUIT AND FIELD PROGRAMMABLE GATE ARRAY 审中-公开
    存储器电路和现场可编程门阵列

    公开(公告)号：US20130215670A1

    公开(公告)日：2013-08-22

    申请号：US13719775

    申请日：2012-12-19

    申请人： Masato ODA ,  Koichiro ZAITSU ,  Kiwamu SAKUMA ,  Shinichi YASUDA ,  Kohei OIKAWA

    发明人： Masato ODA ,  Koichiro ZAITSU ,  Kiwamu SAKUMA ,  Shinichi YASUDA ,  Kohei OIKAWA

    IPC分类号： G11C11/40

    CPC分类号： G11C11/40 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  G11C16/0441 ,  H03K19/1776

    摘要： A memory circuit according to an embodiment includes: a plurality of memory cells each having one pair of first and second nonvolatile memory circuits, each of the first and second nonvolatile memory circuits in each memory cell being capable of making a transition between a high resistance state and a low resistance state, and in a state in which one memory cell in the plurality of memory cells has information stored therein, one of the first and second nonvolatile memory circuits in the one memory cell being in a high resistance state whereas the other being in a low resistance state.

    摘要翻译： 根据实施例的存储器电路包括：多个存储单元，每个存储单元具有一对第一和第二非易失性存储器电路，每个存储单元中的每个第一和第二非易失性存储器电路能够在高电阻状态 和低电阻状态，并且在多个存储单元中的一个存储单元存储有信息的状态下，一个存储单元中的第一和第二非易失性存储器电路之一处于高电阻状态，而另一个存储单元 处于低电阻状态。

    Semiconductor integrated circuit including memory cells having non-volatile memories and switching elements
    8.
    发明授权
    Semiconductor integrated circuit including memory cells having non-volatile memories and switching elements 有权
    包括具有非易失性存储器和开关元件的存储单元的半导体集成电路

    公开(公告)号：US08437187B2

    公开(公告)日：2013-05-07

    申请号：US13232550

    申请日：2011-09-14

    申请人： Shinichi Yasuda ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

    发明人： Shinichi Yasuda ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

    IPC分类号： G11C16/04 ,  G11C7/10

    CPC分类号： H03K19/17728 ,  G11C13/0002 ,  G11C16/0466 ,  H03K19/17768

    摘要： In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.

    摘要翻译： 在一个实施例中，半导体集成电路具有存储单元。 每个存储单元具有非易失性存储器和开关元件。 非易失性存储器和开关元件串联连接在第一电源和第二电源之间。 至少两个存储单元的输出布线彼此连接。 输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。 当输入信号或反相信号被输入时，包括在至少两个存储单元之一中的多个开关元件被断开。 此外，当输入信号或反相信号被输入时，包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。

    MEMORY CIRCUIT USING SPIN MOSFETS, PATH TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, SWITCHING BOX CIRCUIT, SWITCHING BLOCK CIRCUIT, AND FIELD PROGRAMMABLE GATE ARRAY
    9.
    发明申请
    MEMORY CIRCUIT USING SPIN MOSFETS, PATH TRANSISTOR CIRCUIT WITH MEMORY FUNCTION, SWITCHING BOX CIRCUIT, SWITCHING BLOCK CIRCUIT, AND FIELD PROGRAMMABLE GATE ARRAY 有权
    使用旋转MOSFET的存储器电路，具有存储器功能的路径晶体管电路，开关盒电路，开关块电路和现场可编程门阵列

    公开(公告)号：US20120250399A1

    公开(公告)日：2012-10-04

    申请号：US13403308

    申请日：2012-02-23

    申请人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

    发明人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

    IPC分类号： G11C11/16 ,  H03K19/177

    CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

    摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

    摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

    Semiconductor Integrated Circuit
    10.
    发明申请
    Semiconductor Integrated Circuit 有权
    半导体集成电路

    公开(公告)号：US20120230105A1

    公开(公告)日：2012-09-13

    申请号：US13232550

    申请日：2011-09-14

    申请人： Shinichi YASUDA ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

    发明人： Shinichi YASUDA ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

    IPC分类号： G11C16/04 ,  G11C5/06

    CPC分类号： H03K19/17728 ,  G11C13/0002 ,  G11C16/0466 ,  H03K19/17768

    摘要： In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.

    摘要翻译： 在一个实施例中，半导体集成电路具有存储单元。 每个存储单元具有非易失性存储器和开关元件。 非易失性存储器和开关元件串联连接在第一电源和第二电源之间。 至少两个存储单元的输出布线彼此连接。 输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。 当输入信号或反相信号被输入时，包括在至少两个存储单元之一中的多个开关元件被断开。 此外，当输入信号或反相信号被输入时，包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。