公开(公告)号：US08611143B2

公开(公告)日：2013-12-17

申请号：US13403308

申请日：2012-02-23

申请人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

发明人： Hideyuki Sugiyama ,  Masato Oda ,  Shinobu Fujita ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Takao Marukame ,  Tomoaki Inokuchi ,  Yoshiaki Saito

IPC分类号： G11C11/00

CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

公开(公告)号：US20130055189A1

公开(公告)日：2013-02-28

申请号：US13561483

申请日：2012-07-30

申请人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

发明人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5081

摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.

摘要翻译： 在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中 分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线 长度。

公开(公告)号：US08578318B2

公开(公告)日：2013-11-05

申请号：US13561483

申请日：2012-07-30

申请人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

发明人： Kumiko Nomura ,  Shinichi Yasuda ,  Shinobu Fujita ,  Keiko Abe ,  Tetsufumi Tanamoto ,  Kazutaka Ikegami ,  Masato Oda

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5081

摘要： In one embodiment, a method for implementing a circuit design for an integrated circuit includes: (a) obtaining a first wiring to satisfy a given operating frequency; (b) calculating a maximum bypass wiring length based on the given operating frequency and a critical path of the first wiring; (c) obtaining a second wiring by bypassing the first wiring using wires other than wires of the first wiring in a first wiring group, wherein wiring of the integrated circuit is categorized into a plurality of wiring groups, and the first wiring is included in the first wiring group of the categorized wiring groups; and (d) replacing the first wiring with the second wiring, if a difference between the second wiring and the first wiring is not larger than the maximum bypass wiring length, and not replacing the first wiring if said difference is larger than the maximum bypass wiring length.

摘要翻译： 在一个实施例中，一种用于实现集成电路的电路设计的方法包括：（a）获得第一布线以满足给定的工作频率; （b）基于给定的工作频率和第一布线的关键路径计算最大旁路布线长度; （c）通过在第一布线组中使用不同于第一布线的布线的旁路第一布线来获得第二布线，其中集成电路的布线被分类为多个布线组，并且第一布线包括在第一布线中 分类布线组的第一接线组; 以及（d）如果所述第二布线和所述第一布线之间的差不大于所述最大旁路布线长度，则用所述第二布线代替所述第一布线，并且如果所述差大于所述最大旁路布线，则不更换所述第一布线 长度。

公开(公告)号：US20130307054A1

公开(公告)日：2013-11-21

申请号：US13606292

申请日：2012-09-07

申请人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

IPC分类号： H01L27/105

CPC分类号： G11C16/10 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/7881 ,  H01L29/792

摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.

摘要翻译： 一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与 所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

公开(公告)号：US08437187B2

公开(公告)日：2013-05-07

申请号：US13232550

申请日：2011-09-14

申请人： Shinichi Yasuda ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

发明人： Shinichi Yasuda ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： H03K19/17728 ,  G11C13/0002 ,  G11C16/0466 ,  H03K19/17768

摘要： In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.

摘要翻译： 在一个实施例中，半导体集成电路具有存储单元。 每个存储单元具有非易失性存储器和开关元件。 非易失性存储器和开关元件串联连接在第一电源和第二电源之间。 至少两个存储单元的输出布线彼此连接。 输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。 当输入信号或反相信号被输入时，包括在至少两个存储单元之一中的多个开关元件被断开。 此外，当输入信号或反相信号被输入时，包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。

公开(公告)号：US20120230105A1

公开(公告)日：2012-09-13

申请号：US13232550

申请日：2011-09-14

申请人： Shinichi YASUDA ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

发明人： Shinichi YASUDA ,  Masato Oda ,  Kumiko Nomura ,  Keiko Abe ,  Shinobu Fujita

IPC分类号： G11C16/04 ,  G11C5/06

CPC分类号： H03K19/17728 ,  G11C13/0002 ,  G11C16/0466 ,  H03K19/17768

摘要： In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted.

摘要翻译： 在一个实施例中，半导体集成电路具有存储单元。 每个存储单元具有非易失性存储器和开关元件。 非易失性存储器和开关元件串联连接在第一电源和第二电源之间。 至少两个存储单元的输出布线彼此连接。 输入布线与包括在至少两个存储单元中的每一个中的开关元件的控制栅极连接。 当输入信号或反相信号被输入时，包括在至少两个存储单元之一中的多个开关元件被断开。 此外，当输入信号或反相信号被输入时，包括在存储单元之外的至少两个存储单元中的另一个存储单元中的另外多个开关元件导通。

公开(公告)号：US07544223B2

公开(公告)日：2009-06-09

申请号：US11216032

申请日：2005-09-01

申请人： Masato Oda ,  Jun Kakudate ,  Hiroyuki Hamano

发明人： Masato Oda ,  Jun Kakudate ,  Hiroyuki Hamano

IPC分类号： B01D46/18 ,  B01D46/42 ,  F24F1/00

CPC分类号： F24F1/0007 ,  F24F3/1603 ,  F24F2001/0048 ,  F24F2003/1639

摘要： An inner portion of a filter cleaning portion 300 arranged at an inner portion of an interior unit is respectively arranged with cleaning units 300A, 300B constituted by arranging upper brushes 344a, 344b brought into contact with one face of an air filter and lower brushes 322a, 322b brought into contact with other face of the air filter 5 opposedly to each other at filter inlet/outlet 350a, 350b of the filter cleaning portion 300. Further, a longitudinal frame 54 and a transverse frame 55 of an air filter 5 having a filter sheet 51 in a shape of a meshed sheet for catching dust and a frame 52 for supporting the filter sheet 51 are formed on a rear face side (side of heat exchanger 3) of the filter sheet 51.

摘要翻译： 布置在内部单元的内部的过滤器清洁部分300的内部分别布置有清洁单元300A，300B，该清洁单元300A，300B通过布置与空气过滤器的一个面接触的上部电刷344a，344b和下部电刷322a， 322b在过滤器清洁部300的过滤器入口/出口350a，350b处与空气过滤器5的彼此相对的另一面接触。此外，具有过滤器的空气过滤器5的纵向框架54和横向框架55 在过滤片51的背面侧（热交换器3的一侧）上形成有用于捕捉灰尘的网状片状的片材51和用于支撑过滤片51的框架52。

公开(公告)号：US08970249B2

公开(公告)日：2015-03-03

申请号：US13606041

申请日：2012-09-07

申请人： Masato Oda ,  Shinichi Yasuda

发明人： Masato Oda ,  Shinichi Yasuda

IPC分类号： H03K19/173

CPC分类号： G11C5/148

摘要： One embodiment provides a look-up table circuit, including: 2i memories, a half of which constituting a first memory group, the other half of which constituting a second memory group; first to i-th input terminals to which first to i-th input signals are input, respectively; a first output terminal; a switch group that selectively connects one of the memories to the first output terminal according to the first to i-th input signals; a first power-off switch that shuts off power supply to the first memory group in response to one of the first to i-th input signals; and a second power-off switch that shuts off power supply to the second memory group in response to the one of the first to i-th input signals.

摘要翻译： 一个实施例提供了一种查找表电路，包括：2i个存储器，其中一半构成第一存储器组，另一半构成第二存储器组; 分别输入第一至第i输入信号的第一至第i输入端子; 第一输出端子; 开关组，根据第一至第i输入信号有选择地将一个存储器连接到第一输出端; 第一断电开关，其响应于第一至第i输入信号中的一个切断对第一存储器组的电源; 以及第二断电开关，其响应于所述第一至第i输入信号之一而切断对所述第二存储器组的电源。

公开(公告)号：US20060070358A1

公开(公告)日：2006-04-06

申请号：US11216032

申请日：2005-09-01

申请人： Masato Oda ,  Jun Kakudate ,  Hiroyuki Hamano

发明人： Masato Oda ,  Jun Kakudate ,  Hiroyuki Hamano

IPC分类号： B01D46/04

CPC分类号： F24F1/0007 ,  F24F3/1603 ,  F24F2001/0048 ,  F24F2003/1639

摘要： An inner portion of a filter cleaning portion 300 arranged at an inner portion of an interior unit is respectively arranged with cleaning units 300A, 300B constituted by arranging upper brushes 344a, 344b brought into contact with one face of an air filter and lower brushes 322a, 322b brought into contact with other face of the air filter 5 opposedly to each other at filter inlet/outlet 350a, 350b of the filter cleaning portion 300. Further, a longitudinal frame 54 and a transverse frame 55 of an air filter 5 having a filter sheet 51 in a shape of a meshed sheet for catching dust and a frame 52 for supporting the filter sheet 51 are formed on a rear face side (side of heat exchanger 3) of the filter sheet 51.

摘要翻译： 布置在内部单元的内部的过滤器清洁部分300的内部分别布置有通过布置与空气过滤器的一个面接触的上部电刷344a，344b构成的清洁单元300A，300B，以及 下部电刷322a，322b在过滤器清洁部300的过滤器入口/出口350a，350b处与空气过滤器5的彼此相对的另一面接触。 此外，具有过滤器片51的空气过滤器5的纵向框架54和横向框架55形成在用于捕获灰尘的网状片材的形状和用于支撑过滤器片材51的框架52的背面侧 的热交换器3）。

公开(公告)号：US08842475B2

公开(公告)日：2014-09-23

申请号：US13603666

申请日：2012-09-05

申请人： Kosuke Tatsumura ,  Masato Oda ,  Koichiro Zaitsu ,  Atsushi Kawasumi ,  Mari Matsumoto ,  Shinichi Yasuda

发明人： Kosuke Tatsumura ,  Masato Oda ,  Koichiro Zaitsu ,  Atsushi Kawasumi ,  Mari Matsumoto ,  Shinichi Yasuda

IPC分类号： G11C11/34

CPC分类号： G11C16/06 ,  G11C7/06 ,  G11C16/26

摘要： According to one embodiment, a configuration memory includes first and second data lines, a first memory string which comprises at least first and second nonvolatile memory transistors which are connected in series between a common node and the first data line, a second memory string which comprises at least third and fourth nonvolatile memory transistors which are connected in series between the common node and the second data line, and a flip-flop circuit which comprises a first data holding node connected to the common node and a second data holding node connected to a configuration data output node.

摘要翻译： 根据一个实施例，配置存储器包括第一和第二数据线，第一存储器串，其包括串联连接在公共节点和第一数据线之间的至少第一和第二非易失性存储器晶体管，第二存储器串包括 在公共节点和第二数据线之间串联连接的至少第三和第四非易失性存储器晶体管，以及包括连接到公共节点的第一数据保持节点和连接到公共节点的第二数据保持节点的触发器电路 配置数据输出节点。