公开(公告)号：US06724646B2

公开(公告)日：2004-04-20

申请号：US10397409

申请日：2003-03-26

申请人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

发明人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

IPC分类号： G11C1122

CPC分类号： G11C11/22 ,  G11C7/14

摘要： A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.

公开(公告)号：US06707480B2

公开(公告)日：2004-03-16

申请号：US10102633

申请日：2002-03-22

申请人： Minoru Ameyama ,  Satoru Tomita ,  Yasuyuki Shinkai ,  Nekka Matsuura ,  Katsuichi Ohta ,  Naoya Morohoshi ,  Akihisa Itabashi ,  Takanori Yano ,  Katsuhiro Aoki

发明人： Minoru Ameyama ,  Satoru Tomita ,  Yasuyuki Shinkai ,  Nekka Matsuura ,  Katsuichi Ohta ,  Naoya Morohoshi ,  Akihisa Itabashi ,  Takanori Yano ,  Katsuhiro Aoki

IPC分类号： G03G1500

CPC分类号： G03G21/1889 ,  G03G2215/0119 ,  G03G2221/1823

摘要： A plurality of types of engine units which have nonvolatile storage units and which have different performances, respectively, can be attached to an image formation apparatus main body in a replaceable manner. A control unit which controls the performance of an overall apparatus based on information stored in the storage units provided in the engine units, respectively, which are attached to the image formation apparatus main body, is provided in the image formation apparatus main body. Therefore, even if the image formation apparatus main body is common, the performance of the overall apparatus related to recording speed or resolution can be changed only by replacing the engine units different in performance. It is also possible to easily deal with various types of apparatuses.

摘要翻译： 具有非易失性存储单元并且具有不同性能的多种类型的发动机单元可以以可更换的方式附接到图像形成装置主体。 在图像形成装置主体中设置有控制单元，其基于分别安装在图像形成装置主体上的发动机单元中存储的存储单元中的信息来控制整体装置的性能。 因此，即使图像形成装置主体是共同的，也可以通过替换性能不同的发动机单元来改变与记录速度或分辨率有关的整体装置的性能。 也可以容易地处理各种类型的装置。

公开(公告)号：US06587367B1

公开(公告)日：2003-07-01

申请号：US10102418

申请日：2002-03-19

申请人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

发明人： Akitoshi Nishimura ,  Yukio Fukuda ,  Katsuhiro Aoki

IPC分类号： G11C1122

CPC分类号： G11C11/22 ,  G11C7/14

摘要： A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state. As charge sharing takes place between the bias states of the dummy cells and the shorted bitlines, an averaged reference voltage is produced which is substantially centered between the “0” or “1” states. A sense amplifier receives a sense signal from the target memory cell on an associated bitline, and the averaged reference voltage is received on another bitline input of the sense amplifier. Thus, a new ferroelectric memory structure provides a centered reference voltage and a simple sensing scheme for the accurate sensing of the logic state of an FeRAM 1T1C cell for a read operation.

摘要翻译： 铁电存储器结构描述了用于FeRAM存储器件应用的铁电电容器阵列中的1T1C布置。 器件结构为读取FeRAM阵列的目标存储单元的状态的读出放大器提供精确的参考电压和简单的感测方案。 参考电路产生参考电压，其是在多个FeRAM虚拟单元之间共享的电荷的函数。 多个FeRAM虚拟单元中的每个虚拟单元选择性地耦合到多个位线。 参考电路中的短路晶体管将与所选择的目标存储器单元相邻的两个位线或两个位线条耦合。 一个虚拟单元耦合到两个短路位线或位线条中的选择一个，另一个虚设单元耦合到两个短路位线或位线条中的另一个，其中至少一个虚设单元偏置为“0” “状态，并且至少一个其他虚拟单元被偏置到”1“状态。 由于在虚设单元的偏置状态和短路位线之间发生电荷共享，产生基本上以“0”或“1”状态为中心的平均参考电压。 感测放大器在相关联的位线上接收来自目标存储器单元的感测信号，并且平均参考电压在读出放大器的另一位线输入端上被接收。 因此，新的铁电存储器结构提供了居中的参考电压和用于精确检测用于读取操作的FeRAM 1T1C单元的逻辑状态的简单感测方案。

公开(公告)号：US5793600A

公开(公告)日：1998-08-11

申请号：US545980

申请日：1995-10-20

申请人： Yukio Fukuda ,  Katsuhiro Aoki ,  Akitoshi Nishimura ,  Ken Numata

发明人： Yukio Fukuda ,  Katsuhiro Aoki ,  Akitoshi Nishimura ,  Ken Numata

IPC分类号： H01L21/02 ,  H01G4/06 ,  H01G7/00

CPC分类号： H01L28/75 ,  H01L28/60 ,  H01L28/55 ,  Y10T29/435

摘要： A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.

摘要翻译： 包括具有主要组分（Pb）和次要组分（Ti）的PZT铁电层17的电容器和电极结构，形成在铁电层的下侧上并由特殊元素（Pt）和Ti构成的下电极层16 ，及其化合物，以及扩散阻挡层18，其形成在下电极层的下侧，并且用作相对于Pb的扩散阻挡层。 可以是半导体存储器件的组件的电容器和电极结构抑制PZT等中的铁电层的组成的波动，以保持PZT铁电层的预期性能，从而简化和稳定 薄膜制造，并防止电气特性的劣化和对较低层的不利影响。

公开(公告)号：US5776788A

公开(公告)日：1998-07-07

申请号：US601884

申请日：1996-02-15

申请人： Katsuhiro Aoki ,  Yukio Fukuda ,  Akitoshi Nishimura

发明人： Katsuhiro Aoki ,  Yukio Fukuda ,  Akitoshi Nishimura

IPC分类号： C01B13/32 ,  C04B35/49 ,  C23C18/12 ,  H01B3/00 ,  H01G4/12 ,  H01L21/314 ,  H01L21/316 ,  H01L21/70

CPC分类号： H01L21/31691 ,  C23C18/1216 ,  C23C18/1225 ,  C23C18/1254 ,  C23C18/1279 ,  H01L21/02197 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/02356

摘要： A method for forming a PZT strong dielectric film by the sol-gel technique, in which the thickness of the film is substantially no greater than 1000 .ANG.. In another aspect, the drying temperature of the raw material sol-gel solution for forming the PZT dielectric film is maintained within the range of 130.degree.-200.degree. C., and is particularly set lower than the boiling point of the stabilizer contained in the sol-gel raw material and higher than the boiling point of the solvent contained in the sol-gel raw material. As a result of performing the oxidative sintering treatment at a temperature at which perovskite crystals form, it becomes possible to readily form thin films exhibiting a (100) crystal orientation in particular. Additionally, completely crack-free thick films can be formed.

摘要翻译： 通过溶胶 - 凝胶技术形成PZT强电介质膜的方法，其中膜的厚度基本上不大于1000。 在另一方面，用于形成PZT电介质膜的原料溶胶 - 凝胶溶液的干燥温度保持在130℃-200℃的范围内，并且特别设定为低于所述稳定剂的沸点 溶胶凝胶原料，高于溶胶凝胶原料中所含溶剂的沸点。 作为在钙钛矿晶体形成的温度下进行氧化烧结处理的结果，可以容易地形成具有（100）晶体取向的薄膜。 另外，可以形成完全无裂纹的厚膜。

公开(公告)号：US5508953A

公开(公告)日：1996-04-16

申请号：US242924

申请日：1994-05-16

申请人： Yukio Fukuda ,  Katsuhiro Aoki ,  Akitoshi Nishimura ,  Ken Numata

发明人： Yukio Fukuda ,  Katsuhiro Aoki ,  Akitoshi Nishimura ,  Ken Numata

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  G11C11/22

CPC分类号： H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： A capacitor and electrode structure comprising a PZT ferroelectric layer 17 with a primary component (Pb) and secondary component (Ti), a lower electrode layer 16 formed on the underside of the ferroelectric layer and made up of a special element (Pt) and Ti, and compounds thereof, and a diffusion barrier layer 18 which is formed on the underside of the lower electrode layer and which functions as a diffusion barrier with respect to Pb. The capacitor and the electrode structure, which may be a component of a semiconductor memory device, suppress fluctuations in the composition of the ferroelectric layer in PZT, etc., so as to maintain the intended performance of the PZT ferroelectric layer, thereby simplifying and stabilizing film fabrication, and preventing the degradation of electrical characteristics and adverse effects on lower layers.

摘要翻译： 包括具有主要组分（Pb）和次要组分（Ti）的PZT铁电层17的电容器和电极结构，形成在铁电层的下侧上并由特殊元素（Pt）和Ti构成的下电极层16 ，及其化合物，以及扩散阻挡层18，其形成在下电极层的下侧，并且用作相对于Pb的扩散阻挡层。 可以是半导体存储器件的组件的电容器和电极结构抑制PZT等中的铁电层的组成的波动，以保持PZT铁电层的预期性能，从而简化和稳定 薄膜制造，并防止电气特性的劣化和对较低层的不利影响。

公开(公告)号：US5237369A

公开(公告)日：1993-08-17

申请号：US743252

申请日：1991-08-09

申请人： Takayuki Maruta ,  Noboru Sawayama ,  Katsuhiro Aoki

发明人： Takayuki Maruta ,  Noboru Sawayama ,  Katsuhiro Aoki

IPC分类号： G03G15/00 ,  G03G15/02 ,  G03G15/04 ,  G03G15/043 ,  G03G15/06 ,  G03G15/08 ,  G03G21/00

CPC分类号： G03G15/5037 ,  G03G2215/00042

摘要： Color image forming equipment capable of immediately responding to a sharp change in environment and producing stable images over a long period of time. An information value relating to the amount of toner deposition on a photoconductive element which changes with a change in environment and effects the formation of an image with a reference value which defines a first and a second environment. Variable dynamic range control devices each being optimal for respective one of the first and second environments are selectively used on the basis of the result of the above comparison.

摘要翻译： 彩色图像形成设备能够立即响应环境的急剧变化并长时间产生稳定的图像。 与光电元件上的调色剂沉积量相关的信息值，其随着环境变化而变化，并且影响形成具有限定第一和第二环境的参考值的图像。 基于上述比较的结果，选择性地使用对于第一和第二环境中的相应一个环境而优化的可变动态范围控制装置。