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    SYSTEMS AND METHODS FOR ERROR DETECTION IN A MEMORY SYSTEM
    62.
    发明申请
    SYSTEMS AND METHODS FOR ERROR DETECTION IN A MEMORY SYSTEM 有权
    用于记忆系统中错误检测的系统和方法

    公开(公告)号：US20080163032A1

    公开(公告)日：2008-07-03

    申请号：US11619015

    申请日：2007-01-02

    申请人： Luis A. Lastras-Montano

    发明人： Luis A. Lastras-Montano

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1515 ,  G06F11/1044 ,  H03M13/159 ,  H03M13/3715

    摘要： A method for error detection in a memory system. The method includes calculating one or more signatures associated with data that contains an error. It is determined if the error is a potential correctable error. If the error is a potential correctable error, then the calculated signatures are compared to one or more signatures in a trapping set. The trapping set includes signatures associated with uncorrectable errors. An uncorrectable error flag is set in response to determining that at least one of the calculated signatures is equal to a signature in the trapping set.

    摘要翻译： 一种存储系统中的错误检测方法。 该方法包括计算与包含错误的数据相关联的一个或多个签名。 确定错误是否是潜在的可纠正错误。 如果错误是潜在的可纠正错误，则将计算的签名与陷阱集中的一个或多个签名进行比较。 陷阱集包括与不可纠正错误相关联的签名。 响应于确定所计算的签名中的至少一个等于捕获集合中的签名，设置不可校正的错误标志。

    Write bandwidth in a memory characterized by a variable write time
    63.
    发明授权
    Write bandwidth in a memory characterized by a variable write time 有权
    将带宽写入以可变写入时间为特征的存储器中

    公开(公告)号：US08374040B2

    公开(公告)日：2013-02-12

    申请号：US13034936

    申请日：2011-02-25

    申请人： John A. Bivens ,  Michele M. Franceschini ,  Luis A. Lastras-Montano

    发明人： John A. Bivens ,  Michele M. Franceschini ,  Luis A. Lastras-Montano

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1012 ,  G06F2213/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008

    摘要： A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

    摘要翻译： 一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。 存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。 存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。 被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。 数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。 当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。

    Hierarchical error injection for complex RAIM/ECC design
    65.
    发明授权
    Hierarchical error injection for complex RAIM/ECC design 有权
    复杂RAIM / ECC设计的分层错误注入

    公开(公告)号：US08271932B2

    公开(公告)日：2012-09-18

    申请号：US12823010

    申请日：2010-06-24

    申请人： Dean G. Bair ,  Patrick J. Meaney ,  Luis A. Lastras-Montano ,  Alia D. Shah ,  Eldee Stephens

    发明人： Dean G. Bair ,  Patrick J. Meaney ,  Luis A. Lastras-Montano ,  Alia D. Shah ,  Eldee Stephens

    IPC分类号： G06F11/22 ,  G06F17/50

    CPC分类号： G06F11/1008 ,  G06F11/108

    摘要： A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.

    摘要翻译： 一种用于使用分层注入方案来验证RAIM / ECC设计的计算机实现的方法，所述分级注入方案包括选择用于生成错误掩码的标记，基于所选择的标记选择固定位掩码，确定是否将错误注入至少一个标记 通道和至少一个通道的标记芯片; 以及当确定时将错误随机地注入所述标记通道和所述至少一个标记芯片中的至少一个中。

    WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES
    66.
    发明申请
    WEAR-LEVELING AND BAD BLOCK MANAGEMENT OF LIMITED LIFETIME MEMORY DEVICES 有权
    有限寿命内存设备的磨损和边框管理

    公开(公告)号：US20120204071A1

    公开(公告)日：2012-08-09

    申请号：US13445172

    申请日：2012-04-12

    申请人： Bulent Abali ,  John P. Karidis ,  Luis A. Lastras-Montano

    发明人： Bulent Abali ,  John P. Karidis ,  Luis A. Lastras-Montano

    IPC分类号： G11C29/08 ,  G06F11/26

    CPC分类号： G06F12/0246 ,  G06F2212/7211 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/76 ,  G11C29/82

    摘要： Performing wear-leveling and bad block management of limited lifetime memory devices. A method for performing wear-leveling in a memory includes receiving logical memory addresses and applying a randomizing function to the logical memory addresses to generate intermediate addresses within a range of intermediate addresses. The intermediate addresses are mapped into physical addresses of a memory using an algebraic mapping. The physical addresses are within a range of physical addresses that include at least one more location than the range of intermediate addresses. The physical addresses are output for use in accessing the memory. The mapping between the intermediate addresses and the physical addresses is periodically shifted. In addition, contents of bad blocks are replaced with redundantly encoded redirection addresses.

    摘要翻译： 执行有限寿命内存设备的磨损均衡和坏块管理。 用于在存储器中执行磨损均衡的方法包括接收逻辑存储器地址并将随机化功能应用于逻辑存储器地址以在中间地址的范围内生成中间地址。 使用代数映射将中间地址映射到存储器的物理地址。 物理地址在物理地址的范围内，其包括比中间地址的范围至少一个以上的位置。 输出物理地址用于访问存储器。 中间地址和物理地址之间的映射周期性地移位。 此外，坏块的内容被替换为冗余编码的重定向地址。

    ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM
    69.
    发明申请
    ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM 有权
    冗余存储系统中的错误校正和检测

    公开(公告)号：US20110320914A1

    公开(公告)日：2011-12-29

    申请号：US12822503

    申请日：2010-06-24

    申请人： Luiz C. Alves ,  Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

    发明人： Luiz C. Alves ,  Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1004 ,  G06F11/108

    摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.

    摘要翻译： 在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害 失败。

    Computer System and Method of Protection for the System's Marking Store
    70.
    发明申请
    Computer System and Method of Protection for the System's Marking Store 失效
    计算机系统和系统标记商店的保护方法

    公开(公告)号：US20110320911A1

    公开(公告)日：2011-12-29

    申请号：US12825521

    申请日：2010-06-29

    申请人： Richard E. Fry ,  Marc A. Gollub ,  Luis A. Lastras-Montano ,  Eric E. Retter ,  Kenneth L. Wright

    发明人： Richard E. Fry ,  Marc A. Gollub ,  Luis A. Lastras-Montano ,  Eric E. Retter ,  Kenneth L. Wright

    IPC分类号： H03M13/09

    CPC分类号： G06F11/1048

    摘要： A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.

    摘要翻译： 一种用于控制在具有多个核心处理器和eDRAM缓存和互连总线的中央电子复合体中将标记存储更新的方法和装置，用于将服务处理器用于使用内部标记存储器将存储器控制器固件加载到双通道DDR3存储器控制器。 存储器控制器的加载固件负责使用ECC解码器控制来跟踪ECC错误，由此所述标记存储器由慢ECC解码器写入，并且由快速ECC解码器读取，用于所述存储器控制器的每次读取操作，以提供阻塞机制 用于在更新标记存储时通知标记存储固件，并确保标记存储固件无法写入标记存储，直到标记存储固件看到更新，而不会导致标记存储硬件超时。