公开(公告)号：US07735046B2

公开(公告)日：2010-06-08

申请号：US11862523

申请日：2007-09-27

申请人： Igor Arsovski

发明人： Igor Arsovski

IPC分类号： G06F17/50 ,  G06F7/38 ,  H01L25/00 ,  H03K19/173

CPC分类号： G11C17/18 ,  G11C17/165 ,  G11C29/027 ,  G11C29/789

摘要： An e-fuse circuit, a method of programming the e-fuse circuit, and a design structure of the e-fuse circuit. The method includes in changing the threshold voltage of one selected field effect transistor of two field effect transistors connected to different storage nodes of the circuit so as to predispose the circuit place the storage nodes in predetermined and opposite states.

摘要翻译： 电子熔丝电路，e-fuse电路的编程方法以及e-fuse电路的设计结构。 该方法包括改变连接到电路的不同存储节点的两个场效应晶体管的一个选定的场效应晶体管的阈值电压，以便使电路将存储节点放置在预定和相反的状态。

公开(公告)号：US07688610B2

公开(公告)日：2010-03-30

申请号：US12368473

申请日：2009-02-10

申请人： Igor Arsovski ,  Ali Sheikholeslami

发明人： Igor Arsovski ,  Ali Sheikholeslami

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In other words, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits. Significant power reduction without compromising search speed is realized since matchlines carrying a match result are provided with the maximum amount of current.

摘要翻译： 公开了一种低功率匹配线感测方案，其功率根据在匹配线上出现的不匹配比特数分布。 特别地，与具有较少数目不匹配位的匹配决策相比，涉及较大数目不匹配位的匹配决策消耗较少功率。 低功率匹配线感测方案基于预充电到缺失感测架构，并且包括耦合到内容可寻址存储器阵列的每个匹配线的电流控制电路，用于在搜索操作期间监视匹配线的电压电平。 电流控制电路向匹配线的电流源提供电压控制信号，以响应于匹配线的电压来调整施加到匹配线的电流量。 换句话说，由于存在一个或多个失配位而缓慢达到匹配阈值电压的匹配线将比不具有不匹配位的匹配线接收更少的电流。 由于具有匹配结果的匹配线具有最大电流量，所以实现了显着的功率降低而不影响搜索速度。

公开(公告)号：US07515449B2

公开(公告)日：2009-04-07

申请号：US11532233

申请日：2006-09-15

申请人： Igor Arsovski ,  Rahul K. Nadkarni ,  Reid A. Wistort

发明人： Igor Arsovski ,  Rahul K. Nadkarni ,  Reid A. Wistort

IPC分类号： G11C15/00

CPC分类号： G11C15/04 ,  G11C7/02

摘要： This patent describes a method for switching search-lines in a Content Addressable Memory (CAM) asynchronously to improve CAM speed and reduce CAM noise without affecting its power performance. This is accomplished by resetting the match-lines prior to initiating a search and then applying a search word to the search-lines. A reference match-line is provided to generate the timing for the search operation and provide the timing for the asynchronous application of the search data on the SLs. Additional noise reduction is achieved through the staggering of the search data application on the SLs through programmable delay elements.

摘要翻译： 该专利描述了用于在内容寻址存储器（CAM）中异步地切换搜索线以提高CAM速度并降低CAM噪声而不影响其功率性能的方法。 这是通过在发起搜索之前重置匹配线，然后将搜索词应用于搜索线来实现的。 提供参考匹配线以产生用于搜索操作的定时，并为SL上的搜索数据的异步应用提供定时。 通过可编程延迟元件在SL上搜索数据应用的交错来实现额外的降噪。

公开(公告)号：US07511980B2

公开(公告)日：2009-03-31

申请号：US11747428

申请日：2007-05-11

申请人： Igor Arsovski ,  Ali Sheikholeslami

发明人： Igor Arsovski ,  Ali Sheikholeslami

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisions having a lesser number of mismatched bits. The low power matchline sensing scheme is based upon a precharge-to-miss sensing architecture, and includes a current control circuit coupled to each matchline of the content addressable memory array for monitoring the voltage level of the matchline during a search operation. The current control circuit provides a voltage control signal to the current source of the matchline to adjust the amount of current applied to the matchline in response to the voltage of the matchline. In otherwords, matchlines that are slow to reach the match threshold voltage due to the presence of one or more mismatching bits will receive less current than matchlines having no mismatching bits. Significant power reduction without compromising search speed is realized since matchlines carrying a match result are provided with the maximum amount of current.

摘要翻译： 公开了一种低功率匹配线感测方案，其功率根据在匹配线上出现的不匹配比特数分布。 特别地，与具有较少数目不匹配位的匹配决策相比，涉及较大数目不匹配位的匹配决策消耗较少功率。 低功率匹配线感测方案基于预充电到缺失感测架构，并且包括耦合到内容可寻址存储器阵列的每个匹配线的电流控制电路，用于在搜索操作期间监视匹配线的电压电平。 电流控制电路向匹配线的电流源提供电压控制信号，以响应于匹配线的电压来调整施加到匹配线的电流量。 换句话说，由于存在一个或多个失配位而缓慢达到匹配阈值电压的匹配线将比不具有不匹配位的匹配线接收更少的电流。 由于具有匹配结果的匹配线具有最大电流量，所以实现了显着的功率降低而不影响搜索速度。

公开(公告)号：US20070075731A1

公开(公告)日：2007-04-05

申请号：US11163015

申请日：2005-09-30

申请人： Igor Arsovski ,  Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

发明人： Igor Arsovski ,  Hayden Cranford ,  Joseph Iadanza ,  Sebastian Ventrone

IPC分类号： H03K19/003

CPC分类号： H03K19/00346

摘要： An integrated circuit device includes functional logic, an anti-noise machine, and state monitoring points providing the anti-noise machine with an interface to the functional logic for monitoring states of the functional logic. The anti-noise machine includes indicia defining noise precursor states for the functional logic, and recognition logic coupled to the state monitoring points. The anti-noise machine is operable to generate anti-noise responsive to the recognition logic detecting in the functional logic noise precursor states matching the indicia.

摘要翻译： 集成电路设备包括功能逻辑，抗噪声机器和状态监测点，其为抗噪声机器提供与用于监视功能逻辑状态的功能逻辑的接口。 抗噪声机器包括定义用于功能逻辑的噪声前导状态的标记，以及耦合到状态监测点的识别逻辑。 抗噪声机器可操作以响应于与标记匹配的功能逻辑噪声前导状态中的识别逻辑检测产生抗噪声。

公开(公告)号：US20130223161A1

公开(公告)日：2013-08-29

申请号：US13403252

申请日：2012-02-23

申请人： Igor Arsovski ,  George M. Braceras ,  Harold Pilo

发明人： Igor Arsovski ,  George M. Braceras ,  Harold Pilo

IPC分类号： G11C7/10

CPC分类号： G11C5/147 ,  G11C11/417

摘要： An integrated circuit structure comprises a static random access memory (SRAM) structure and a logic circuit. A power supply is operatively connected to the SRAM structure, and provides a first voltage to the SRAM structure. A voltage limiter is operatively connected to the power supply. The voltage limiter comprises a switching device operatively connected to the power supply. The switching device receives the first voltage and a second voltage supplied to structures external to the SRAM structure. A resistive element is operatively connected to the switching device. The switching device connects the resistive element to the power supply. The resistive element is selected to enable an output from the switching device to the logic circuit when a difference between the first voltage and the second voltage is greater than a voltage threshold value of the switching device.

摘要翻译： 集成电路结构包括静态随机存取存储器（SRAM）结构和逻辑电路。 电源可操作地连接到SRAM结构，并且向SRAM结构提供第一电压。 电压限制器可操作地连接到电源。 电压限制器包括可操作地连接到电源的开关装置。 开关器件接收提供给SRAM结构外部结构的第一电压和第二电压。 电阻元件可操作地连接到开关装置。 开关装置将电阻元件连接到电源。 电阻元件被选择为当第一电压和第二电压之间的差大于开关器件的电压阈值时，使能从开关器件到逻辑电路的输出。

公开(公告)号：US08214699B2

公开(公告)日：2012-07-03

申请号：US12147670

申请日：2008-06-27

申请人： Igor Arsovski ,  David J. Wager ,  Michael A. Ziegerhofer

发明人： Igor Arsovski ,  David J. Wager ,  Michael A. Ziegerhofer

IPC分类号： G11C29/12

CPC分类号： G06F13/4243

摘要： Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal. Thus, in the performance screening mode, the digital integrated circuit is effectively converted into a performance screen ring oscillator (PSRO), the output of which can be monitored to determine whether performance criteria for the digital integrated circuit are met.

摘要翻译： 公开了具有数字集成电路的半导体芯片，例如存储器件（例如，静态随机存取存储器（SRAM）阵列，动态随机存取存储器（DRAM）阵列，内容可寻址存储器（CAM）阵列等）），其可以 选择性地在功能模式或性能筛选模式下操作。 在功能模式中，使用由外部信号发生器提供的第一信号来激活电路中的第一设备，并且作为响应，电路中的第二设备输出数据输出信号。 在演奏屏蔽模式中，第二信号由内部信号发生器基于数据输出信号内部产生。 然后该第二信号用于激活电路中的第一设备，并且作为响应，第二设备输出数据输出信号。 因此，在性能筛选模式下，数字集成电路被有效地转换为性能屏幕环形振荡器（PSRO），其输出可以被监视以确定是否满足数字集成电路的性能标准。

公开(公告)号：US20120134221A1

公开(公告)日：2012-05-31

申请号：US13366804

申请日：2012-02-06

申请人： Igor Arsovski ,  Matthew W. Deming ,  Darryl R. Hill ,  Harold Pilo ,  Reid A. Wistort

发明人： Igor Arsovski ,  Matthew W. Deming ,  Darryl R. Hill ,  Harold Pilo ,  Reid A. Wistort

IPC分类号： G11C7/10

CPC分类号： G11C8/08 ,  G11C11/413

摘要： A dual word-line level shifter circuit and associated SRAM. A circuit is disclosed that includes a first transistor gated by a data input at the lower voltage, and a second transistor gated by a restore input at the higher voltage, wherein the first and second transistors are coupled along a series path to a source at the higher voltage; a control node along the series path; an output node coupled to the control node via a first pair of parallel transistors; and a feedback circuit having a second pair of parallel transistors and a feedback transistor, wherein the feedback transistor couples the second pair of parallel transistors to the control node and is gated by the output node.

摘要翻译： 双字线电平移位电路和相关SRAM。 公开了一种电路，其包括通过较低电压的数据输入门控的第一晶体管和由较高电压的恢复输入门控的第二晶体管，其中第一和第二晶体管沿串联路径耦合到源极 电压较高; 沿着串行路径的控制节点; 输出节点，经由第一对并联晶体管耦合到所述控制节点; 以及具有第二对并联晶体管和反馈晶体管的反馈电路，其中所述反馈晶体管将所述第二对并联晶体管耦合到所述控制节点并由所述输出节点门控。

公开(公告)号：US20120075918A1

公开(公告)日：2012-03-29

申请号：US12892160

申请日：2010-09-28

申请人： Igor Arsovski ,  John A. Fifield ,  Robert M. Houle ,  Harold Pilo

发明人： Igor Arsovski ,  John A. Fifield ,  Robert M. Houle ,  Harold Pilo

IPC分类号： G11C11/00 ,  G11C8/08 ,  G06F17/50

CPC分类号： G11C8/08 ,  G11C11/413

摘要： An integrated circuit that includes memory containing wordlines and bitcells having SRAM storage elements and being connected to the wordlines. Wordline up-level assist circuitry is provided that is designed and configured to provide a plurality of selectable voltage values that can be selected to provide the wordline up-level voltage that is provided to the bitcells during a memory read cycle and/or write cycle. In one example, the voltage value selected is selected based on characterization of the as-fabricated bitcells so as to decrease the likelihood of the bitcells experiencing a stability failure.

摘要翻译： 一种集成电路，包括含有字线的存储器和具有SRAM存储元件并连接到字线的位单元。 提供了字线上级辅助电路，其设计和配置为提供多个可选择的电压值，其可被选择以提供在存储器读周期和/或写周期期间提供给位单元的字线上电压。 在一个示例中，所选择的电压值基于所制造的比特单元的表征来选择，以便降低位单元经历稳定性故障的可能性。

公开(公告)号：US20120049947A1

公开(公告)日：2012-03-01

申请号：US12862310

申请日：2010-08-24

申请人： Igor Arsovski ,  Bruce Balch ,  Umberto Garofano ,  Nazmul Habib

发明人： Igor Arsovski ,  Bruce Balch ,  Umberto Garofano ,  Nazmul Habib

IPC分类号： H01L25/00 ,  G06F17/50 ,  G01R29/26

CPC分类号： G06F17/5036 ,  G01R29/26 ,  G06F2217/82

摘要： A method and device for measuring integrated circuit power supply noise and calibration of power supply noise analysis models. The method includes collecting power supply noise monitor data from an integrated circuit having one or more power supply noise monitors connected between a power supply and respective scan cells of a scan chain and one or more functional circuits connected to the scan chain by scanning a power supply noise generation pattern into the scan chain and scanning a resultant pattern out of the scan chain; converting the resultant data into actual values of selected power supply parameters; generating simulated values of the selected power supply parameters using a power supply noise simulation model based on design data of the integrated chip; comparing the actual values of the selected power supply parameters to the simulated values of the selected power supply parameters; and modifying the power supply noise simulation model based on the comparing.

摘要翻译： 一种用于测量集成电路电源噪声和电源噪声分析模型校准的方法和装置。 该方法包括从具有连接在扫描链的电源和相应扫描单元之间的一个或多个电源噪声监视器的集成电路收集电源噪声监视数据，以及通过扫描电源连接到扫描链的一个或多个功能电路 将扫描链中的噪声产生模式扫描到扫描链中; 将得到的数据转换成所选择的电源参数的实际值; 使用基于集成芯片的设计数据的电源噪声模拟模型生成所选择的电源参数的模拟值; 将所选择的电源参数的实际值与所选择的电源参数的模拟值进行比较; 并根据比较修改电源噪声仿真模型。