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公开(公告)号：US6093324A
公开(公告)日：2000-07-25
申请号：US242028
申请日：1999-02-24
CPC分类号： C07K16/065 , B01J41/20
摘要： A method for the purification or recovery of immunoglobulins from plasma or other immunoglobulin-containing material is disclosed which includes subjecting the plasma or other immunoglobulin-containing material to chromatographic fractionation on a macroporous anion-exchange resin to recover an immunoglobulin-containing fraction therefrom.
摘要翻译： PCT No.PCT / AU97 / 00498 Sec。 一九九九年二月二十四日 102（e）1999年2月24日PCT 1997年8月7日PCT PCT。 公开号WO98 / 05686 日期：1998年2月12日公开了一种从血浆或其他含有免疫球蛋白的材料纯化或回收免疫球蛋白的方法，其包括使血浆或其它含有免疫球蛋白的材料在大孔阴离子交换树脂上进行色谱分级以回收免疫球蛋白 - 含有部分。
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64.发明授权
公开(公告)号：US06058050A
公开(公告)日：2000-05-02
申请号：US291019
申请日：1999-04-14
申请人： John Wu , Lidong Chen , Peter B. Gillingham
发明人： John Wu , Lidong Chen , Peter B. Gillingham
IPC分类号： G11C7/00 , G11C8/08 , G11C11/408
CPC分类号： G11C8/08 , G11C11/4085
摘要： The invention relates to word line drivers found in embedded dynamic random access memories (DRAM) of application specific integrated circuits (ASICs). The invention is a method of programming the time at which the boosted voltage interval begins, and the period during which the boosted voltage is maintained. The result is the ability to apply the boosted voltage only when needed, thus minimizing the danger to the oxide integrity. The method comprises initiating an active row cycle in response to a leading edge of a row activation signal, initiating a precharge cycle in response to a trailing edge of the row activation signal, the precharge cycle comprising a broad line boost interval initiated by the falling edge of the row activation signal and having a predetermined duration controlled by a programmable delay circuit.
摘要翻译： 本发明涉及在专用集成电路（ASIC）的嵌入式动态随机存取存储器（DRAM）中发现的字线驱动器。 本发明是一种编程升压电压间隔开始的时间和保持升压电压的时间的方法。 结果是仅在需要时施加升压电压的能力，从而最小化对氧化物完整性的危害。 该方法包括响应于行激活信号的前沿响应于行激活信号的后沿启动预充电周期，该预充电周期包括由下降沿引发的宽线升压间隔 并具有由可编程延迟电路控制的预定持续时间。
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公开(公告)号：US5959903A
公开(公告)日：1999-09-28
申请号：US904153
申请日：1997-07-31
申请人： Lidong Chen , Arun Achyuthan , John Wu
发明人： Lidong Chen , Arun Achyuthan , John Wu
IPC分类号： G11C11/408 , G11C29/00 , G11C7/00
CPC分类号： G11C29/846 , G11C11/408 , G11C11/4087
摘要： This invention describes a column redundancy method and apparatus in a DRAM that minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required in repairing faulty columns. The invention discloses a DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for energizing appropriate memory columns in response to the decoder memory addresses received at an input thereof; redundant column drivers; and switch means for steering the decoded memory address onto one of either normal or redundant column driver paths. The invention further illustrates a fusing system which minimizes the capacitance of redundant select lines, thereby removing unnecessary delay in the redundant column path.
摘要翻译： 本发明描述了DRAM中的列冗余方法和装置，其使正常和冗余列路径之间的定时差最小化，并且使修复故障列所需的保险丝数量最小化。 本发明公开了一种具有以行和列排列的存储器元件的DRAM，存储器元件可通过解码施加到其上的存储器地址来访问，正常列驱动器响应于在其输入处接收的解码器存储器地址来激励适当的存储器列; 冗余列驱动程序; 以及用于将解码的存储器地址转向正常或冗余列驱动器路径之一的开关装置。 本发明进一步示出了使冗余选择线的电容最小化的融合系统，从而消除冗余列路径中的不必要的延迟。
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公开(公告)号：US5835438A
公开(公告)日：1998-11-10
申请号：US773770
申请日：1996-12-24
申请人： John Wu , Lidong Chen , Peter B. Gillingham
发明人： John Wu , Lidong Chen , Peter B. Gillingham
IPC分类号： G11C7/00 , G11C8/08 , G11C11/408
CPC分类号： G11C8/08 , G11C11/4085
摘要： A method of driving a DRAM word line comprising initiating a word line active cycle from a leading edge of a row enable signal, applying a first voltage to a word line following and as a result of said leading edge, receiving a trailing edge of the enable signal and applying a boosted voltage to the word line following and as a result of the trailing edge.
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